Never mind, I’ve worked it out now. I sign- or zero-extend the operand elements depending on whether it’s vaadd or vaaddu, do the addition, then shift and round the result. Gives a sensible answer

Section 3.8 provides the following details to clarify the behavior: Does this help?

I’m somewhat unclear on the intended semantics for the vector fixed-point averaging add/sub instructions. The description is “The averaging add and subtract instructions right shift the result by

The meeting minutes in added in the note. You can also find it under riscv-admin/rvv-intrinsics.

Hi all, A reminder that the next open meeting to discuss on the RISC-V V C Intrinsic API v1.0 is going to be held later on 2023/03/20 6AM (GMT -7) / 11PM (GMT +8). The agenda can be found in the

Ah, I had a dim recollection of seeing mention of this, but overlooked it when asking my question. Thanks for the reminder. All good now. Cheers, PA

Thanks for reminder, Nick, Krste

Rationale is still there: it's the last Note in Section 10.1 https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#101-vector-arithmetic-instruction-encoding

This was intentional, though the rationale seems to have dropped out of text. The goal was to simplify reading of assembly code, where product inputs were kept together at beginning of instruction

Hi all, I’m looking at sections 11.10, 11.12, and 11.14 in the V extension spec, version 1.0. The order of operands vs1/rs1 and vs2 appears to be reversed in the assembler for the multiply-add

Hi all, A reminder that the next open meeting to discuss on the RISC-V V C Intrinsic API v1.0 is going to be held later on 2022/02/23 6AM (GMT -7) / 11PM (GMT +8). The agenda can be found in the

The meeting minutes in added in the note. You can also find it under riscv-admin/rvv-intrinsics.

Hi all, A reminder that the next open meeting to discuss on the RISC-V V C Intrinsic API v1.0 release is going to be held later on 2022/02/02 6AM (GMT -7) / 11PM (GMT +8). The agenda can be found in

We are delighted to announce the start of the public review period for the following proposed standard extensions to the RISC-V ISA: Zvfh Zvfhmin The review period begins today, January 24, 2023 and

The meeting minutes in added in the note. You can also find it under riscv-admin/rvv-intrinsics.

Hi all, A reminder that the next open meeting to discuss on the RISC-V V C Intrinsic API v1.0 release is going to be held on 2023/01/05 6AM (GMT -7) / 11PM (GMT +8). The agenda can be found in the

also please note the unified discovery effort is underway. i am adding in philipp and aaron to the chain. Mark -------- sent from a mobile device. please forgive any typos.

We generally want to avoid using CSRs for runtime discovery, instead preferring a user-accessible data structure provided by the runtime system. Under Linux, there is a user API to figure out the

Yeah, Rich's interpretation was right; see https://lists.riscv.org/g/tech-crypto-ext/message/856

I actually interpreted Krste's statement differently. Not necessarily correctly. It sounded to me like there wasn't enough room in the current vector encoding space to fit possible extensions, so the