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Re: Smaller embedded version of the Vector extension
Software should still work with VLEN>=64 if written correctly, as it should be VLEN agnostic.
Maybe it should be a recommendation that VLEN>=128, with a minimum of 64 for app processors?
Lower
Software should still work with VLEN>=64 if written correctly, as it should be VLEN agnostic.
Maybe it should be a recommendation that VLEN>=128, with a minimum of 64 for app processors?
Lower
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By
Tony Cole
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#634
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Re: Smaller embedded version of the Vector extension
This is the requirement for app processors, which are not generally small cores.
Most competing SIMD extensions are at least 128b per vector register.
Lower performance on codes that work well on
This is the requirement for app processors, which are not generally small cores.
Most competing SIMD extensions are at least 128b per vector register.
Lower performance on codes that work well on
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By
Krste Asanovic
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#633
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Re: Smaller embedded version of the Vector extension
What is the advantage to RVV requiring VLEN >= 128?
I think this should be changed to VLEN >= 64 because:
1) VLEN = 64 is more likely for small implementations; creating a
mandatory expectation to
What is the advantage to RVV requiring VLEN >= 128?
I think this should be changed to VLEN >= 64 because:
1) VLEN = 64 is more likely for small implementations; creating a
mandatory expectation to
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By
Guy Lemieux
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#632
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Re: Smaller embedded version of the Vector extension
see github issue #550
Krste
see github issue #550
Krste
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By
Krste Asanovic
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#631
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Re: Smaller embedded version of the Vector extension
This is a good question.
So if the RVM22 profile requires VLEN=32, ELEN=64, LMUL=8 then the vector registers will have the same amount of state as ARM MVE.
Tariq
This is a good question.
So if the RVM22 profile requires VLEN=32, ELEN=64, LMUL=8 then the vector registers will have the same amount of state as ARM MVE.
Tariq
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By
Tariq Kurd <tariq.kurd@...>
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#630
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Re: 答复: [RISC-V] [tech-vector-ext] Smaller embedded version of the Vector extension
Hi, Krste:
The RISC-V V TG have the plan to support a lowcost vector extension in RVMxx profile?
Best Regards
Shaofei
2021.6.3
-----邮件原件-----
发件人: krste@...
Hi, Krste:
The RISC-V V TG have the plan to support a lowcost vector extension in RVMxx profile?
Best Regards
Shaofei
2021.6.3
-----邮件原件-----
发件人: krste@...
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By
Shaofei (B)
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#629
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Re: Smaller embedded version of the Vector extension
Hi Tony,
All of the vector permutation instructions can be simulated using the memory system. For example, vslide can be simulated by storing the vector register and loading it at an offset; vrgather
Hi Tony,
All of the vector permutation instructions can be simulated using the memory system. For example, vslide can be simulated by storing the vector register and loading it at an offset; vrgather
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By
Nick Knight
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#628
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Re: Smaller embedded version of the Vector extension
Hi Bruce,
Do you mean vrgather instead of vslide?
I use vrgather_vx_* and vslidedown to perform a vector element rotate (and other things), see:
Hi Bruce,
Do you mean vrgather instead of vslide?
I use vrgather_vx_* and vslidedown to perform a vector element rotate (and other things), see:
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By
Tony Cole
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#627
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Re: Smaller embedded version of the Vector extension
| could an extension just change state like the number of vector registers?
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Don't understand tbis question - please elaborate.
Krste
| could an extension just change state like the number of vector registers?
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Don't understand tbis question - please elaborate.
Krste
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By
Krste Asanovic
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#626
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Re: Smaller embedded version of the Vector extension
Thanks, I must have missed this bit:
"4.5. Mapping with LMUL > 1 and ELEN > VLEN
If vector registers are grouped to support larger SEW, with ELEN > VLEN, the vector registers in the group are
Thanks, I must have missed this bit:
"4.5. Mapping with LMUL > 1 and ELEN > VLEN
If vector registers are grouped to support larger SEW, with ELEN > VLEN, the vector registers in the group are
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By
Tony Cole
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#625
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Re: Smaller embedded version of the Vector extension
Section 4.5,
Krste
| On Wed, Jun 2, 2021 at 8:38 AM Andrew Waterman <andrew@...> wrote:
| It’s actually not fundamental to the ISA design that VLEN >= ELEN. An
| implementation with
Section 4.5,
Krste
| On Wed, Jun 2, 2021 at 8:38 AM Andrew Waterman <andrew@...> wrote:
| It’s actually not fundamental to the ISA design that VLEN >= ELEN. An
| implementation with
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By
Krste Asanovic
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#624
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Re: Smaller embedded version of the Vector extension
could an extension just change state like the number of vector registers?
could an extension just change state like the number of vector registers?
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By
mark
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#623
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Re: Smaller embedded version of the Vector extension
We do allow supported SEW to vary with LMUL, so implementation can
support single-width operations on SEW=64. See section 4.5,
Krste
| So, (on a 32x 32-bit vector register machine) the widening and
We do allow supported SEW to vary with LMUL, so implementation can
support single-width operations on SEW=64. See section 4.5,
Krste
| So, (on a 32x 32-bit vector register machine) the widening and
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By
Krste Asanovic
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#622
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Re: Smaller embedded version of the Vector extension
The VLEN>=128 constraint is only for the application processor "V"
extension for the app profile - not for embedded vectors which can
have VLEN=32.
From spec Introduction:
'
The term base vector
The VLEN>=128 constraint is only for the application processor "V"
extension for the app profile - not for embedded vectors which can
have VLEN=32.
From spec Introduction:
'
The term base vector
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By
Krste Asanovic
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#621
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Re: Smaller embedded version of the Vector extension
It seems that restriction of minimum LMUL=2 would be half number of vector registers and LMUL=4 would be 8 vector registers.
Thang
From: tech-vector-ext@... <tech-vector-ext@...>On Behalf Of Tariq
It seems that restriction of minimum LMUL=2 would be half number of vector registers and LMUL=4 would be 8 vector registers.
Thang
From: tech-vector-ext@... <tech-vector-ext@...>On Behalf Of Tariq
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By
Thang Tran
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#620
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Re: Smaller embedded version of the Vector extension
Hi Bruce,
“I an not a fan of the vslide instructions. It seems they expose the size of the vector registers in a very unfortunate way. In particular they break down if VLEN=1. Most code would be
Hi Bruce,
“I an not a fan of the vslide instructions. It seems they expose the size of the vector registers in a very unfortunate way. In particular they break down if VLEN=1. Most code would be
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By
Tony Cole
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#619
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Re: Smaller embedded version of the Vector extension
I think the concern here is lack of a clearly defined data layout pattern for such cases.
eg, should the LSBs be in the odd or even register half, or should it be implementation-defined?
Guy
I think the concern here is lack of a clearly defined data layout pattern for such cases.
eg, should the LSBs be in the odd or even register half, or should it be implementation-defined?
Guy
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By
Guy Lemieux
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#618
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Re: Smaller embedded version of the Vector extension
For widening and narrowing instructions to work, the V spec depends upon changing SEW (to EEW) and LMUL (to EMUL), such that EEW/EMUL == SEW/LMUL. That is, to change the element size (widen or
For widening and narrowing instructions to work, the V spec depends upon changing SEW (to EEW) and LMUL (to EMUL), such that EEW/EMUL == SEW/LMUL. That is, to change the element size (widen or
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By
Guy Lemieux
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#617
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Re: Smaller embedded version of the Vector extension
It’s actually not fundamental to the ISA design that VLEN >= ELEN. An implementation with VLEN=32 could support SEW=64 whenever LMUL >= 2. This approach starts to pose code-generation headaches, but
It’s actually not fundamental to the ISA design that VLEN >= ELEN. An implementation with VLEN=32 could support SEW=64 whenever LMUL >= 2. This approach starts to pose code-generation headaches, but
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By
Andrew Waterman
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#616
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Re: Smaller embedded version of the Vector extension
OK, so it seems that to run our software (which Tony Cole referred to) we need VLEN>=64 for our embedded application.
Is there any scope for reducing the number of V registers? Could RV32E_Vmin have
OK, so it seems that to run our software (which Tony Cole referred to) we need VLEN>=64 for our embedded application.
Is there any scope for reducing the number of V registers? Could RV32E_Vmin have
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By
Tariq Kurd <tariq.kurd@...>
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#615
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