I would suggest filing an issue in the riscv/riscv-gnu-toolchain github tree. Put something like vector or rvv in the issue title to make it clear it is a vector related issue. The gcc support is

Hi all, I’m still new to RISC-V and the Vector extensions, so forgive me if I’ve missed something, the following have been fixed or noted before. Also, am I sending this to the correct

Hi Vector Team, I’m new to RISC-V and the Vector extensions, so forgive me if I’ve missed something. I have searched the specs, emails and git hub issues, but not found anything on

I haven’t seen any burning issues come by, and am still trying to clean up spec. So unless someone has agenda items, I’m canceling meeting tomorrow, Krste

I’m still working on spec cleanup and I don’ t have any major outstanding issues to discuss, so will cancel the TG meeting this week. Please bring up any burning issues on this mailing

Date: 2021/03/26 Task Group: Vector Extension Chair: Krste Asanovic Vice-Chair: Roger Espasa Number of Attendees: ~10 Current issues on github: https://github.com/riscv/riscv-v-spec A short meeting

We'll meet again in usual slot. The main discussion topic will be #545. Please read the issue thread on github. Summary: The proposal is to move vector AMOs from their current encoding to leave

Date: 2021/03/19 Task Group: Vector Extension Chair: Krste Asanovic Vice-Chair: Roger Espasa Number of Attendees: ~16 Current issues on github: https://github.com/riscv/riscv-v-spec Issues

There are a few issues to discuss, so we’ll meet in the regular time slot on the calendar, Krste

I'm cancelling meeting again, as I still have not been able to clean spec. I realize it will be more efficient for folks to wait for a clean version for a complete read through. Few issues are

I'm still working through spec cleanup. The list and github has been quiet, and I have no new issues to raise, so I suggest we cancel this meeting and push out for a week. Krste

Date: 2021/02/19 Task Group: Vector Extension Chair: Krste Asanovic Vice-Chair: Roger Espasa Number of Attendees: ~23 Current issues on github: https://github.com/riscv/riscv-v-spec # Next

Thanks Krste, I’ve put exactly that I the spec. Tariq

We’ll meet today in usual slot, details on Google calendar Agenda is to discuss any issues found while reading over the v0.10 spec. List and GitHub has been quite quiet, so this might be a short

If you check over the vector instruciton listing table It’s all the instructions in funct3=OPFVF with an F in the operand column. Most of these are missing. Krste

Hi everyone, I’ve updated the Zfinx spec to show which V-extension instructions are affected. https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc#vector Please review the

For hardware with very long vector registers, the same effect might be accomplished by having a custom way to change VLMAX dynamically (across all harts, etc.). It would seem that would cover a

| in terms of overlap with that case — that case normally selects maximally sized AVL. the implied goals there are to make best use of vector register capacity and | throughput. l | i’m

in terms of overlap with that case — that case normally selects maximally sized AVL. the implied goals there are to make best use of vector register capacity and throughput. l i’m suggesting a

| I agree with you. | I had suggested the mapping of 00000 to an implementation-defined value (chosen by the CPU architect). For some architectures, this may be 16, for others it may | be 32, or even