I concur. Software can effect tail-undisturbed by A pre conditioning the load, B loading into temp register then use bitwise logic into target, C save last byte of target , lde1, read last byte, write

On the issue of what bits to load for vle1.v, we need to decide whether these are byte loads of length ceil(vl/8) or whether they are bit loads of length vl. Bit loads _can_ have the additional

Hi Krste, This mask loading instruction is exactly the one we look forward. I got some confusion on hiccups, why machines with internal dynamic data striping require hiccups whenever used as a mask?

Date: 2020/12/04 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscv-v-spec Note: No meeting

Next meeting today in usual time slot as on calendar, Krste Date: 2020/11/20 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~17 Current issues on

That is exactly what I want. Thanks Mark. Weiwei 发件人: tech-vector-ext@... <tech-vector-ext@...>代表 mark 发送时间: 2020年11月25日 23:13 收件人: Wang Weiwei

If you are looking for expected dates they are always in the spec status spreadsheet at: https://docs.google.com/spreadsheets/d/1iDXsvDhu8uRtiss0YazlioBBEV9Jrq_o01E59QdmkE0/edit?usp=sharing if it is

Hi Krste and Andrew, What is the rough plan for rvv v1.0 release? I searched vector-ext mailing list but can’t find the info I want. Thanks Weiwei

I think we'll be spending a chunk of time on mask layout and implementation issues. See you then, Krste

👍

This is issue #601. It was pointed out that *e7 (estimate to 7 bits) suffix on mnemonic is easily confused with e32 (element size 32) on other mnemonics. This is probably one we can handle on email

Date: 2020/11/13 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~22 Current issues on github: https://github.com/riscv/riscv-v-spec Issues

Because there is no "official" BF16 standard (beyond interchange format) and because other vendors have made incompatible choices (so no de-facto standard either), we will need to define the RISC-V

In support of Open Source Software and publicly released modeling schemes, does the Vector Task Group have a recommendation for arithmetic reference? The published ISSs can provide checking results

Also, reminder we'll be meeting tomorrow (Friday Nov 13) as per calendar entry (7 hours from now), Krste Date: 2020/11/06 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger

This sounds right to me as well. No use making a special case for strided stores with rs2=x0. Bill On 11/9/20 12:04 PM, Nick Knight wrote:

I understand now. I'm on board iff the memory consistency model experts assent.

There’s a comment about this in spec already. But note that this would be in a case where you're relying on having multiple accesses in a non-deterministic order to one memory location, which is

Sorry, slightly off topic, but what was the rationale for I guess I'm thinking about the possibility of a toolchain relaxing `li, x1, 0; inst x1` into `inst x0`.

I made an error copied from my meeting notes - this should be when rs2=x0 (i.e., the stride value), Krste