any possible compatibility issues (i can't see any but not sure) in this one with existing implementations like you discussed in the first one? Mark -------- sent from a mobile device. please

The second fix is just a clarification of a missing case in the spec: "vsetvl[i] with rd=rs1=x0 is reserved if vill was 1 beforehand." The "vsetvl[i] x0, x0" form is defined in terms of whether

A few issues have been identified in corners of the vector spec. The first change was an error of omission in not catching some cases of source and destination register overlap that can not be

The meeting minutes in added in the note. You can also find it under riscv-admin/rvv-intrinsics.

Sorry for the late notice, the zoom link was updated (which we are now using the one hosted by RVI). Meeting link: https://zoom.us/j/96312719575 Passcode: 494823 Join link:

Hi all, A reminder that the next open meeting to discuss on the RISC-V V C Intrinsic API v1.0 release is going to be held on 2022/10/31 7AM (GMT -7) / 10PM (GMT +8). The agenda can be found in the

From: Krste Asanovic via lists.riscv.org Sent: Thursday, October 6, 2022 12:42 PM We can delay, but not prevent, the need to have greater than 32b instructions. I worked on another RISC ISA

We can delay, but not prevent, the need to have greater than 32b instructions. All general-purpose architectures with a large set of vector instructions have >32b instructions (although ARM and POWER

| This proposal is only for BF16. Should we look forward to proposals | from DLFloat, TF16, and others? Yes. | Won't this overly encumber the ISA, | like the ever-growing list of SIMD

Hi all, There is a very active effort from IEEE. I hope some one from RISC-V group can join IEEE P3109 as a stakeholder. I see Ken being active in both the RISC-V and P3109. I am pleased to report

Hi, (apologies for the repeated message I am using the web interface due to some problems with our email and I think I just replied to Guy) We're looking at something like this so we can support two

This proposal is only for BF16. Should we look forward to proposals from DLFloat, TF16, and others? Won't this overly encumber the ISA, like the ever-growing list of SIMD instructions? It seems like

https://github.com/riscv/riscv-bfloat16 | Hi Krste, | On 3/10/22 23:15, Krste Asanovic wrote: || There is a proposal in progress to add scalar/vector BF16, so it is || exaggerating to say we are

Hi Krste, Is this already in some public document? Do you have a link handy? Thanks a lot. Kind regards, Roger -- Roger Ferrer Ibáñez - roger.ferrer@... Barcelona Supercomputing Center -

| bfloat16 is arguably just as important as binary16 encoding. | This makes me wonder: | a) assigning the term "half precision" to binary16 encoding gives it a | "here first" monopoly and leaves

bfloat16 is arguably just as important as binary16 encoding. This makes me wonder: a) assigning the term "half precision" to binary16 encoding gives it a "here first" monopoly and leaves bfloat16

The meeting minute is updated in the document of the Google calendar link.

These RISC-V vector extensions to handle IEEE FP16 were defined prior to ratification of the vector specification, but were left out of RVV 1.0 as they were not to be included in the base V

+sig-vector@...

Hi all, A reminder that an open meeting to draft the RISC-V V C Intrinsic API v1.0 release is going to be held later on 2022/10/03 7AM (GMT -7) / 10PM (GMT +8). Slide has been posted and agenda is in