Bill you said element 9, but did you mean element labeled "a" which is the 11th element in the vector? (I agree with that). However, I would NOT agree that a masked out element has been written, even

Here's where the "implementation" cost comes in (at least in our implementation; others, of course, may have more clever ways of doing this) -> If you pick "vl=3", then the vstart and vltrim

The way the discussion has been going, I think either would be permissible. Not only that, but it would have been permissible for element 9 already to have been overwritten with 1's (if vma allows

Here's a question for the group: I did in as a picture... hopefully it will go through the mailing list:

The mask could be built with sew=16, as the mask is ordinal based. And there are tricks to set it up, for example a direct load (register move) to v0 to set the correct bit. The mask could be built

Hi, what is a reasonable sequence to insert an element into an arbitrary position in the vector? I considered the following sequence (assume the input vector is v12) vid.v v1 vmseq.vx v0, v1,

The forward progress is to advance to another task. In the case of machine mode it can potentially "resolve" the cause of the vl=0 return and re-execute the loop (without the overhead of the

| First I am very happy that "arbitrary decisions by the | micro-architecture" allow reduction of vl to any [non-zero] value. | Even if such appear "random". [...] | A check for vl=0 on platforms

First I am very happy that "arbitrary decisions by the micro-architecture" allow reduction of vl to any [non-zero] value. Even if such appear "random". Exactly. I see this openness/lack of

I agree, however, it still does not answer the ISA visible behavioural question: "Is the trap allowed to set vl=0 on return?" Can this be compliant behaviour for certain platforms? If so, then it

Date: 2020/10/9 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscv-v-spec # 576 vlsegff

Date: 2020/10/2 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed; #

(sending replies to vector list - as this is off topic for CMOs) My opinion is that baking SIMT execution model into ISA for purposes of exposing microarchitectural performance (i.e., cache

My take is the same as Andrew has outlined below. Bill On 10/15/20 4:30 PM, andrew@... wrote:

Yep, it's sufficient for the needs of while loop Vectorization. It is suboptimal for "SIMT on vector". For that you need a completion mask. and it is far too late to add that to the

Forwarding this to tech-vector-ext; couple comments below. Indeed, I've found other microarchitectural reasons to favor this approach (e.g., speculating through mask-register values). Enumerating all

Per calendar instructions, in usual time slot, Proposed agenda: #560 vmulh rounding mode #576 vlsegff exception behavior #550 names/contents of initial vector subsets #568 disabling/context swtiching

Vector Extension Task Group Meeting When: Friday, 12 June 2020 8:00am to 9:00am (UTC-07:00) America/Los Angeles Repeats: Weekly on Friday, through Thursday, 8 October 2020 Organizer: Krste

Done. Thanks Roger. From: Roger Espasa <roger.espasa@...> Date: Sunday, October 4, 2020 at 12:49 PM To: Joseph Rahmeh <Joseph.Rahmeh@...> Cc: "tech-vector-ext@..." <tech-vector-ext@...>, Robert

Joseph, May I suggest you open a git issue here: https://github.com/riscv/riscv-v-spec/issues with these two questions? It will help better tracking and will ensure whatever the resolution is, it does