
Vector TG meeting minutes 2020/7/31 meeting
Apologies for delay in sending these out. When doing this week's
minutes, I realized I hadn't sent out previous week's.
Krste
Date: 2020/7/31
Task Group: Vector Extension
Chair: Krste
Apologies for delay in sending these out. When doing this week's
minutes, I realized I hadn't sent out previous week's.
Krste
Date: 2020/7/31
Task Group: Vector Extension
Chair: Krste

By
Krste Asanovic
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#322
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Re: Integer Overflow/Saturation Operations
For extended precision arithmetic, e.g. such as is often performed in cryptography, 2X widening multiply accumulate is the best that I have found. (And as far as I know other members
For extended precision arithmetic, e.g. such as is often performed in cryptography, 2X widening multiply accumulate is the best that I have found. (And as far as I know other members

By
Andy Glew Si5
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#321
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Re: Fixed Point (Chapter 13): Clarification Request
Thank you for the response, Andrew.
Given that these operations are intended to be conveniences, in the first place (hence: vector), the addition of a required macro for inclusion could be considered
Thank you for the response, Andrew.
Given that these operations are intended to be conveniences, in the first place (hence: vector), the addition of a required macro for inclusion could be considered

By
CDS <cohen.steed@...>
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#320
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Re: Fixed Point (Chapter 13): Clarification Request
Having implemented these instructions recently, I can say they weren’t unduly onerous to provide, and the HW cost increase wasn’t that great (the rounding and clipping logic are new; the rest
Having implemented these instructions recently, I can say they weren’t unduly onerous to provide, and the HW cost increase wasn’t that great (the rounding and clipping logic are new; the rest

By
Andrew Waterman
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#319
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Re: vrsub.vi, used as negation
Would be mostly redundant with vadd.vi, since the immediate operand is signed. (Same reason the scalar ISA doesn’t provide a subi instruction.)
Would be mostly redundant with vadd.vi, since the immediate operand is signed. (Same reason the scalar ISA doesn’t provide a subi instruction.)

By
Andrew Waterman
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#318
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vrsub.vi, used as negation
Is the point of vrsub.vi to provide negation? From a compiler/user perspective, completing the vsub pattern with vsub.vi (even as a virtual instruction) may be a usability enhancement to consider.
Is the point of vrsub.vi to provide negation? From a compiler/user perspective, completing the vsub pattern with vsub.vi (even as a virtual instruction) may be a usability enhancement to consider.

By
CDS <cohen.steed@...>
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#317
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Integer Overflow/Saturation Operations
Vectorwidening multiply & accumulate instructions:
These instructions, signed or unsigned, will quickly overflow in even simple cases.
Given absence of flagging (e.g. OVERFLOW), a saturating version
Vectorwidening multiply & accumulate instructions:
These instructions, signed or unsigned, will quickly overflow in even simple cases.
Given absence of flagging (e.g. OVERFLOW), a saturating version

By
CDS <cohen.steed@...>
·
#316
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Fixed Point (Chapter 13): Clarification Request
The definition of the numeric range (at the beginning of section 13) matches the definition of an integer, not of a fixedpoint number. For example, the range specified is the range of an integer,
The definition of the numeric range (at the beginning of section 13) matches the definition of an integer, not of a fixedpoint number. For example, the range specified is the range of an integer,

By
CDS <cohen.steed@...>
·
#315
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Re: [riscv/riscvvspec] For V1.0  Make unsigned scalar integer in widening instructions 2 * SEW (#427) (and signed)
great!
again this is meant as informational for when this goes to vote.
this should be discussable now in email with questions and comments.
please include this in the ratification materials (place in
great!
again this is meant as informational for when this goes to vote.
this should be discussable now in email with questions and comments.
please include this in the ratification materials (place in

By
mark
·
#314
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Re: [riscv/riscvvspec] For V1.0  Make unsigned scalar integer in widening instructions 2 * SEW (#427) (and signed)
I filled out the RISCV Policy: Change and Extension Rationale
as best I could for the issue #427. I believe it is accessible by all. But I will also paste the contents below.
I filled out the RISCV Policy: Change and Extension Rationale
as best I could for the issue #427. I believe it is accessible by all. But I will also paste the contents below.

By
David Horner
·
#313
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Proposed WG: RISC V needs CMOs, and hence a CMO Working Group
RISC V needs CMOs, and hence a CMO Working Group
EditNew Page
RISC V needs CMOs, and hence a CMO Working Group
EditNew Page

By
Andy Glew Si5
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#312
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[riscv/riscvvspec] For V1.0  Make unsigned scalar integer in widening instructions 2 * SEW (#427) (and signed)
I posted a comment to the closed #427
Not everyone subscribes to GitHub, so I post it below,
I am requesting this proposal be reconsidered/reevaluated for V1.0 inclusion in
I posted a comment to the closed #427
Not everyone subscribes to GitHub, so I post it below,
I am requesting this proposal be reconsidered/reevaluated for V1.0 inclusion in

By
David Horner
·
#311
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Re: VFRECIP/VFRSQRT instructions
On 8/3/20 1:41 PM, Andrew Waterman wrote:
I agree with your computation with a really tiny difference (I get that it just barely rounds to 2^7.32040). I can't say why I got 37 when I did it 810
On 8/3/20 1:41 PM, Andrew Waterman wrote:
I agree with your computation with a really tiny difference (I get that it just barely rounds to 2^7.32040). I can't say why I got 37 when I did it 810

By
Bill Huffman
·
#310
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Re: VFRECIP/VFRSQRT instructions
Thanks for validating against your table, Bill.
With my value for that entry, the worst error on the interval of interest is 2^7.32041, for input 0x3f1a0000. With yours, it's 2^7.3164 for
Thanks for validating against your table, Bill.
With my value for that entry, the worst error on the interval of interest is 2^7.32041, for input 0x3f1a0000. With yours, it's 2^7.3164 for

By
Andrew Waterman
·
#309
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Re: VFRECIP/VFRSQRT instructions
The recip table matches mine as does the worst case error.
I have one different entry in the square root table. For entry 77, where you have 36, I have 37. I'm not sure whether it matters. Also,
The recip table matches mine as does the worst case error.
I have one different entry in the square root table. For entry 77, where you have 36, I have 37. I'm not sure whether it matters. Also,

By
Bill Huffman
·
#308
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Re: VFRECIP/VFRSQRT instructions
Now annotated version detail
https://github.com/DavidHorner/recip/blob/master/vrecip.cc
For the 7x7 below notice the biased value does not exceed 21 for recip (5 of 7 bits) and 15
Now annotated version detail
https://github.com/DavidHorner/recip/blob/master/vrecip.cc
For the 7x7 below notice the biased value does not exceed 21 for recip (5 of 7 bits) and 15

By
David Horner
·
#307
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Re: VFRECIP/VFRSQRT instructions
I should have said that my results are for the 7/7 case. And it sounds like we're in agreement then. We probably have the same table.
Bill
On 8/2/20 9:50 AM, DSHORNER wrote:
I should have said that my results are for the 7/7 case. And it sounds like we're in agreement then. We probably have the same table.
Bill
On 8/2/20 9:50 AM, DSHORNER wrote:

By
Bill Huffman
·
#306
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Re: VFRECIP/VFRSQRT instructions
This is the link to the revised code that does n by m LUT
https://github.com/DavidHorner/recip/blob/master/vrecip.cc
On 20200801 4:51 p.m., David Horner via
This is the link to the revised code that does n by m LUT
https://github.com/DavidHorner/recip/blob/master/vrecip.cc
On 20200801 4:51 p.m., David Horner via

By
David Horner
·
#305
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Re: VFRECIP/VFRSQRT instructions
What I initially posted was a compilation from days previously, and I pulled in some bogus test results.
Here is a fresh run :
./a.out 7 5 ;./a.out 7 6 ;./a.out 7 7 ;./a.out 7 8
What I initially posted was a compilation from days previously, and I pulled in some bogus test results.
Here is a fresh run :
./a.out 7 5 ;./a.out 7 6 ;./a.out 7 7 ;./a.out 7 8

By
David Horner
·
#304
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Re: VFRECIP/VFRSQRT instructions
David,
Here are a series of statements leading to my worst case answer:
For the mantissa range 0xF5_0000 to 0xF5_FFFF, the reciprocal estimate is 0x85_0000
The largest error is for 0xF5_0000
The
David,
Here are a series of statements leading to my worst case answer:
For the mantissa range 0xF5_0000 to 0xF5_FFFF, the reciprocal estimate is 0x85_0000
The largest error is for 0xF5_0000
The

By
Bill Huffman
·
#303
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