tech-vector-ext@lists.riscv.org

Home Messages Hashtags Subgroups

Messages

Between

and

Re: Fixed Point (Chapter 13): Clarification Request

perhaps i am not upto date on this topic. but addresses are fixed point. (integers). and you need vector support for vector loads using the vector accumulators.(indexs). the math, other than

By swallach · #327 ·

Re: Integer Overflow/Saturation Operations

Andy, Thank you for your response. The concern I'm raising is less about "How do I avoid overflow?" and more about "Why are we avoiding the specification of saturating instructions, or an overflow

By CDS <cohen.steed@...> · #326 ·

Re: Fixed Point (Chapter 13): Clarification Request

Perhaps, it is important to understand the history of why fixed point is utilized. Historically, fixed point was the alternative for expensive floating point implementations/operations, or was the

By CDS <cohen.steed@...> · #325 · Edited

Re: Fixed Point (Chapter 13): Clarification Request

| Thank you for the response, Andrew. | Given that these operations are intended to be conveniences, in the first place (hence: vector), the | addition of a required macro for inclusion could be

By Krste Asanovic · #324 ·

Vector TG minutes for 2020/8/7 meeting

Date: 2020/8/7 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~22 Current issues on github: https://github.com/riscv/riscv-v-spec Issues

By Krste Asanovic · #323 ·

Vector TG meeting minutes 2020/7/31 meeting

Apologies for delay in sending these out. When doing this week's minutes, I realized I hadn't sent out previous week's. Krste Date: 2020/7/31 Task Group: Vector Extension Chair: Krste

By Krste Asanovic · #322 ·

Re: Integer Overflow/Saturation Operations

For extended precision arithmetic, e.g. such as is often performed in cryptography, 2X widening multiply accumulate is the best that I have found. (And as far as I know other members

By Andy Glew Si5 · #321 ·

Re: Fixed Point (Chapter 13): Clarification Request

Thank you for the response, Andrew. Given that these operations are intended to be conveniences, in the first place (hence: vector), the addition of a required macro for inclusion could be considered

By CDS <cohen.steed@...> · #320 ·

Re: Fixed Point (Chapter 13): Clarification Request

Having implemented these instructions recently, I can say they weren’t unduly onerous to provide, and the HW cost increase wasn’t that great (the rounding and clipping logic are new; the rest

By andrew@... · #319 ·

Re: vrsub.vi, used as negation

Would be mostly redundant with vadd.vi, since the immediate operand is signed. (Same reason the scalar ISA doesn’t provide a subi instruction.)

By andrew@... · #318 ·

vrsub.vi, used as negation

Is the point of vrsub.vi to provide negation? From a compiler/user perspective, completing the vsub pattern with vsub.vi (even as a virtual instruction) may be a usability enhancement to consider.

By CDS <cohen.steed@...> · #317 ·

Integer Overflow/Saturation Operations

Vector-widening multiply & accumulate instructions: These instructions, signed or unsigned, will quickly overflow in even simple cases. Given absence of flagging (e.g. OVERFLOW), a saturating version

By CDS <cohen.steed@...> · #316 ·

Fixed Point (Chapter 13): Clarification Request

The definition of the numeric range (at the beginning of section 13) matches the definition of an integer, not of a fixed-point number. For example, the range specified is the range of an integer,

By CDS <cohen.steed@...> · #315 ·

Re: [riscv/riscv-v-spec] For V1.0 - Make unsigned scalar integer in widening instructions 2 * SEW (#427) (and signed)

great! again this is meant as informational for when this goes to vote. this should be discussable now in email with questions and comments. please include this in the ratification materials (place in

By mark · #314 ·

Re: [riscv/riscv-v-spec] For V1.0 - Make unsigned scalar integer in widening instructions 2 * SEW (#427) (and signed)

I filled out the RISC-V Policy: Change and Extension Rationale as best I could for the issue #427. I believe it is accessible by all. But I will also paste the contents below.

By David Horner · #313 ·

Proposed WG: RISC V needs CMOs, and hence a CMO Working Group

RISC V needs CMOs, and hence a CMO Working Group EditNew Page

By Andy Glew Si5 · #312 ·

[riscv/riscv-v-spec] For V1.0 - Make unsigned scalar integer in widening instructions 2 * SEW (#427) (and signed)

I posted a comment to the closed #427 Not everyone subscribes to GitHub, so I post it below, I am requesting this proposal be reconsidered/re-evaluated for V1.0 inclusion in

By David Horner · #311 ·

Re: VFRECIP/VFRSQRT instructions

On 8/3/20 1:41 PM, Andrew Waterman wrote: I agree with your computation with a really tiny difference (I get that it just barely rounds to 2^-7.32040). I can't say why I got 37 when I did it 8-10

By Bill Huffman · #310 ·

Re: VFRECIP/VFRSQRT instructions

Thanks for validating against your table, Bill. With my value for that entry, the worst error on the interval of interest is 2^-7.32041, for input 0x3f1a0000. With yours, it's 2^-7.3164 for

By andrew@... · #309 ·

Re: VFRECIP/VFRSQRT instructions

The recip table matches mine as does the worst case error. I have one different entry in the square root table. For entry 77, where you have 36, I have 37. I'm not sure whether it matters. Also,

By Bill Huffman · #308 ·

561 - 580 of 887

Home Hashtags Subgroups Terms