Krste, Yes, I double checked and you are right. Padding OpenCL vectors to POT is fine. In terms of the instructions affected by the element groups semantics, I see three cases: - dot (this was already

Hi all, A reminder that an open meeting to draft the RISC-V V C Intrinsic API v1.0 release is going to be held on next Monday 2022/09/05 7AM (GMT -7) / 10PM (GMT +8). The planned agenda will be to

| Krste, | Sorry it took me a long time to provide feedback. | Yes, this is the kind of feature we could need for graphics and GPGPU-style SIMT. Many thanks for taking the | time to think about how

Krste, Sorry it took me a long time to provide feedback. Yes, this is the kind of feature we could need for graphics and GPGPU-style SIMT. Many thanks for taking the time to think about how the idea

Hi all, As mentioned in the first RFC letter, here we want to share our draft roadmap for the formal release. The main goal of this release is to stablize the using environment of the RVV C

Hi all, We (SiFive) are going to draft out a formal v1.0 release for the RVV C intrinsic API. Next week we are going to provide a roadmap, including time reserved for comments on what is left on the

Krste has requested that this group not be archived due to pending work on Zvfh and Zvfhmin extensions. Based on this, we will wait until this work completes to proceed with

Community members, The Vector Extension Task Group community has completed its work and is slated to be deactivated and archived on August 15, 2022. If you believe that this decision has been made in

Hi Peter: Discovery ABI/API are discussed in another place, which might not be part of psABI, it would be more like Linux specific stuffs, SiFive folks and Rivos folks have some discussion about the

Hi Zalman: Define a standardized vector ABI means we can have a common interface and agreement among different compiler and libraries, isn't means we must use that everywhere, we did have several way

If you're in a hurry, Imperas has developed a set of vector tests also, and they're likely very comprehensive. I don't know which configurations are supported though.

First of all, discussion of libc functions such as strcmp is irrelevant to this thread, as they do not have vector register arguments. They pass pointers to arguments in memory and use (and always

I would like to emphasize Zalman Stern's point about trading off hardware economy for dynamic software optimization, in the context of a larger comment about optimizing compiled code for RISC-V. The

A plea to not design the future around vague and ill-considered use cases... A fundamental issue here is that a vector unit built for high performance computing will potentially have a massive amount

Hi Jan: Thanks for your amazing work! I think that it is very useful, it saves us time to re-implement those functions with RVV :)

Hi Kito, Might this implementation of math functions be helpful? It already supports RVV via intrinsics.

Hi: I am Kito from the RISC-V psABI group, we've defined a basic vector ABI, which allows function use vector registers within function, that could be used for optimize several libraries like libc,

FYI: https://github.com/riscv-software-src/riscv-tests/pull/400 <alexander.podoplelov@...> wrote:

Also, could you please inform me about RISC-V Vector compliance tests v1.0? 25.07.2022 13:52, Umer Shahid пишет:

Great, thanks for letting me know. Regards, Umer -- Umer Shahid Member Technical Staff 10xEngineers Mobile: +92-334-4072836 Email: umer.shahid@..., umershahid@...,pk