tech-vector-ext@lists.riscv.org

Home Messages Hashtags Subgroups

Messages

Between

and

Re: Vector TG meeting minutes 2020/4/03

These are basic operations, not application kernels. It's easy to call out missing instructions when considering individual operations. It's more important to gather and evaluate actual application

By Krste Asanovic · #87 ·

the usage of Vector AMO Operations

Hi, all I have a problem about the usage of VectorAMO Operations. In the spec, there is only two sentences to describe the usageof Vector AMO Operations. Who have the concrete sample or other

By Linjie Yu · #86 ·

Re: 答复: [RISC-V] [tech-vector-ext] Vector TG meeting minutes 2020/4/03

Hi, Nick That is a good suggestion for my code, thank you very much. But I develop my code depend on spec 0.7.1. The q-wide instructions had not been added to the spec. And I am confused with the

By Linjie Yu · #85 ·

Re: 答复: [RISC-V] [tech-vector-ext] Vector TG meeting minutes 2020/4/03

I agree with your point. But nowadays, the spec is not stable, and there is no target SOC to verify it. So, in my opinion, the number of instructions is an important indicator at present. 发件人:

By Linjie Yu · #84 ·

Re: Vector TG meeting minutes 2020/4/03

Hi Damon, Thanks for providing a concrete example! I think you can improve the performance of your first example (non-widening loads). Instead of immediately widening, you could instead perform your

By Nick Knight · #83 ·

Re: Vector TG meeting minutes 2020/4/03

The number of instructions does not necessarily correspond to the speed, and especially not to the PPA or efficiency. Making the load/store simpler might save enough area to make it as or more energy

By Bruce Hoult · #82 ·

Re: 答复: [RISC-V] [tech-vector-ext] Vector TG meeting minutes 2020/4/03

Hi，all I have some applications about byte/halfword/word vector load/stores, like gemm, direct convolution and son on. For 3x3 direct convolution, the code without byte/halfword/word

By Linjie Yu · #81 ·

Re: Vector TG meeting minutes 2020/4/03

I agree Nick. So here is a suggestion, not completely facetiously: For load byte/half/word example when SEW = 64 An implementation can

By David Horner · #80 ·

Re: Vector TG meeting minutes 2020/4/03

In scalar code, there is always signed/zero extension for the data and alignment. I do not see a different with vector load/store. If alignment is needed, not much additional cost for signed/zero

By Thang Tran · #79 ·

Re: Vector TG meeting minutes 2020/4/03

Bob Dreyer said he would share an example code. Do you really have a 2x or 4x wider write port to the vector register file to make vlb and the like work at full memory bandwidth? If yes, what is the

By Alex Solomatnikov · #78 ·

Re: Vector TG meeting minutes 2020/4/03

Hi Nick, It is confidential customer application code. Thanks, Thang

By Thang Tran · #77 ·

Re: Vector TG meeting minutes 2020/4/03

Hi Thang, Can you, and anyone else who responds, please be concrete about the applications you have in mind? I tried to do so in my email. In my opinion, concrete examples are crucial to making an

By Nick Knight · #76 ·

Re: Vector TG meeting minutes 2020/4/03

There are real application (mixed integer/FP - convert instruction is used) codes written with load/store byte/halfword/word. There is a huge performance impact by adding widening instruction in a

By Thang Tran · #75 ·

Re: Vector TG meeting minutes 2020/4/03

On GitHub, this is Issue #362. While I'm generally in favor of dropping them, I am aware it will pose a challenge to several applications if, additionally, indexed loads and stores switch to

By Nick Knight · #74 ·

Vector TG meeting minutes 2020/4/03

Date: 2020/4/03 Task Group: Vector Extension Chair: Krste Asanovic Number of Attendees: ~15 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed: #354/362 The following

By Krste Asanovic · #73 ·

meeting reminder

We will be meeting again this morning. I hope to focus on closing on features for upcoming 0.9 release. Krste

By Krste Asanovic · #72 ·

Re: A couple of questions about the vector spec

Yes - agreed. I believe it is going to be considered for support in the 64 bit encoding. Best regards Nagendra

By Nagendra Gulur · #71 ·

Re: A couple of questions about the vector spec

On #2, it would require finding a 2 bit field in the vector load format to encode "no-scaling/2/4/8". Not trivial within the 32b format. On Wed, Mar 11, 2020 at 1:30 AM Nagendra Gulur

By Roger Espasa · #70 ·

Re: A simple fractional LMUL proposal

On 2020-03-24 11:40 p.m., Krste Asanovic wrote: I attempt to summarize the needs here: 1) to reduce the register pressure that successive levels of LMUL invoke (halving

By David Horner · #69 ·

Re: Vector Indexed Loads - Partial Return?

Not really challenge :-) But it's the only option if you can't / don't want to add a "vstart" equivalent (because you don't want to save/restore it...) @Nagendra: note that the spec does require the

By Roger Espasa · #68 ·

801 - 820 of 887

Home Hashtags Subgroups Terms