Hi everyone, I’ve updated the Zfinx spec to show which V-extension instructions are affected. https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc#vector Please review the list, and tell m

Thanks Krste, I’ve put exactly that I the spec. Tariq

Hi everyone, Are there any plans for a cut-down configuration of the vector extension suitable for embedded cores? It seems that the 32x128-bit register file is suitable for application class cores bu

OK, so it seems that to run our software (which Tony Cole referred to) we need VLEN>=64 for our embedded application. Is there any scope for reducing the number of V registers? Could RV32E_Vmin have 1

This is a good question. So if the RVM22 profile requires VLEN=32, ELEN=64, LMUL=8 then the vector registers will have the same amount of state as ARM MVE. Tariq