First there is currently no ff gather. But if there were, the vl would need to be truncated to the first in sequence that faulted. That would potentially require back tracking by the handler from the

The trap if first address bad is stipulated behaviour. The other are not specified in the vector extension , but 1. the counter is part of the generalized performance spec. 2. Always trap but allow re

that should have been "The HS is in control, it can "leak" or not as it sees fit" obviously.

The VS having this awareness can be very beneficial. It allows the OS to better manage its resources. It can switch to handling other supervisory actions while that data is paged/staged in. Never the

yes. I will below. It could depending upon what implementation details are designed into the hart. Control Mechanisms: If the first address of the vector load is problematic, whether first fault or no

However, we did discuss its merit; if it would trump the encoding dificulties, see below - there are two aspects here - a) checking array indexes are within bounds, which absent proof that the indexes

I am curious as well. It makes sense when the whole vector is participating and masking is the only means to limit processing, but we have vlen. Specifically no First Fault variant was included so tha

Yes, absolutely. Many vector models historically have been co-processors with their own internal status. RVV integration is also a major accomplishment. I was a part of that. However, a consensus with

Thank you for this very important consideration. Yes. The expectation is that many of the current constraints will be relaxed in future versions. It is here that I most appreciate your interest. I hav

I apparently missed the meeting that I thought was at noon eastern. There are of course the remaining open for v1.0 issues. I gather what was discussed was if we could reasonably move to public review

For discussion: The text states: reporting an error and terminating execution is the appropriate response. Issue #598 to be resolved after v1.0 and issue #364 which is tagged with "resolve for v1.0" a

I am disappointed that the meeting was cancelled. I am concerned that jnk0le's contributions/concerns, in particular, have been dismissed and to the extent that they were objections to the draft have

@guy: I don't know what each letter stands for, but the link has this: TRN1 Interleave even elements from two vectors . I assume there is TRN for odds and maybe mixed?

Andrew Waterman called Thursday and we discussed many issues including challenges with Issues in Github. We determined that both were unaware of some relevant aspects [neither of us intentionally blin

Excellent. Congratulations, and thank you!!

Can we see the git of your work? Does this mean the 32 vector registers are not enough, or that the number of elements for the given input vector length are not enough? Note vdot.vv is experimental. I

I concur. Software can effect tail-undisturbed by A pre conditioning the load, B loading into temp register then use bitwise logic into target, C save last byte of target , lde1, read last byte, write

That is one approach. It is a consideration that has recently been mentioned wrt misa. I remember Luke Kenneth Casson Leighton <lkcl@...> was in on the discussions. A variety of csr and related a

My take: This is analogous to ascii(7-bit) and EBCIDIC(8-bit) both competing in the 8 bit byte addressable character space. Initial solutions were fragmentation, then code pages (select-able character

These are all important considerations. However, what they have in common when considering Allen's question: is that they are all tactical considerations are in the context of our current framework of