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about masked-off bits for instructions vmsbf.m, vmsif.m, vmsof.m #defines

Hi， I have a question about masked-off bits. I am not sure what is the behavior of destination inactive masked-off bits for instructions vmsbf.m, vmsif.m, vmsof.m. Does the "xxxx" means we can fill an

By lilei2@... ·

#defines

GCC RISC-V Vector Intrinsic Instructions and #defines missing 3 #defines

Hi Tony: Could you create issues on github to track that? https://github.com/riscv/riscv-gcc Thanks :)

By Kito Cheng ·

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