vsetvli x1, x0, e8, m8 vsetvli x0, x0, e16, m8 Alex

One option is to allow mask generating instructions (compares) to write either to regular vector regs or to vmask and to provide move instructions between vector regs and vmask. But mask consuming ins

If separate loads and stores are introduced for mask, then separate vmask register can be introduced to avoid dual use of v0 (as a regular vector register and as a mask register) and its complications

Guy, FPGA energy/power data is not really relevant to general purpose ISA design, unless your goal is to design an ISA only for soft FPGA cores like Nios or MicroBlaze. Please, take a look at the pape

Code bloat is important - not just the number load and store instructions but also additional vsetvl/i instructions. This was one of the reasons for vle8, vle16 and others. LMUL>1 is also great for en

Bob Dreyer said he would share an example code. Do you really have a 2x or 4x wider write port to the vector register file to make vlb and the like work at full memory bandwidth? If yes, what is the i

I suggest to treat fractional LMUL as a negative power of 2: 1/2 = 2^-1, 1/4 = 2^-2 Already LMUL == 2^vtype.vlmul , so no changes needed for all values of vtype.vlmul that are already in the spec. Ale