
Internal review of Zvfhmin/Zvfh extensions before public review
Hi, (apologies for the repeated message I am using the web interface due to some problems with our email and I think I just replied to Guy) We're looking at something like this so we can support two f
Hi, (apologies for the repeated message I am using the web interface due to some problems with our email and I think I just replied to Guy) We're looking at something like this so we can support two f

By
Roger Ferrer Ibanez
· #837
·


Internal review of Zvfhmin/Zvfh extensions before public review
Hi Krste, Is this already in some public document? Do you have a link handy? Thanks a lot. Kind regards, Roger
Hi Krste, Is this already in some public document? Do you have a link handy? Thanks a lot. Kind regards, Roger

By
Roger Ferrer Ibanez
· #834
·


回复：Re: 回复：[RISCV] [techvectorext] RISCV Vector Spec version 1.0rc120210608
Hi, I didn't realise this was the private list and Romain is not in this one. So I'm forwarding his answer on his behalf Hope this helps. Kind regards,
Hi, I didn't realise this was the private list and Romain is not in this one. So I'm forwarding his answer on his behalf Hope this helps. Kind regards,

By
Roger Ferrer Ibanez
· #648
·


回复：Re: 回复：[RISCV] [techvectorext] RISCV Vector Spec version 1.0rc120210608
Hi, I agree that computing those indexes is not always trivial Some ideas you can consider (not claiming these are the most efficient ways) reverse is not too complex: vid.v + vrsub.vx using vl as the
Hi, I agree that computing those indexes is not always trivial Some ideas you can consider (not claiming these are the most efficient ways) reverse is not too complex: vid.v + vrsub.vx using vl as the

By
Roger Ferrer Ibanez
· #646
·


回复：[RISCV] [techvectorext] RISCV Vector Spec version 1.0rc120210608
Hi Linjie, I'm not sure I understood your question. I think a vid.v (with a vl of your choice) that then you (logical) shift right 1 bit (vsrl.vi) would generate an index like the one you have now the
Hi Linjie, I'm not sure I understood your question. I think a vid.v (with a vl of your choice) that then you (logical) shift right 1 bit (vsrl.vi) would generate an index like the one you have now the

By
Roger Ferrer Ibanez
· #643
·


Check mask all ones / all zeros
Hi Guy, The code I've been looking at, uses this for a branch. FWIW: this is the SLEEF library (vector math library). An example of how it uses the check can be found at https://github.com/shibatch/sl
Hi Guy, The code I've been looking at, uses this for a branch. FWIW: this is the SLEEF library (vector math library). An example of how it uses the check can be found at https://github.com/shibatch/sl

By
Roger Ferrer Ibanez
· #604
·


Check mask all ones / all zeros
Hi Andrew, thanks for the prompt and insightful answer. I'll use vpopc.m then. Indeed, my question was motivated while looking at some code that operates on whole registers but it can definitely be ge
Hi Andrew, thanks for the prompt and insightful answer. I'll use vpopc.m then. Indeed, my question was motivated while looking at some code that operates on whole registers but it can definitely be ge

By
Roger Ferrer Ibanez
· #599
·


Check mask all ones / all zeros
Hi all, I could not find any instruction that immediately computes this. Apologies if I missed the obvious here. Two options came to mind: vpopc.m and check whether the result is 0 (all zeros) or VLMA
Hi all, I could not find any instruction that immediately computes this. Apologies if I missed the obvious here. Two options came to mind: vpopc.m and check whether the result is 0 (all zeros) or VLMA

By
Roger Ferrer Ibanez
· #597
·


Sequence to insert an element
Hi, what is a reasonable sequence to insert an element into an arbitrary position in the vector? I considered the following sequence (assume the input vector is v12) vid.v v1 vmseq.vx v0, v1, <index>
Hi, what is a reasonable sequence to insert an element into an arbitrary position in the vector? I considered the following sequence (assume the input vector is v12) vid.v v1 vmseq.vx v0, v1, <index>

By
Roger Ferrer Ibanez
· #460
·


EEW and nonindexed loads/stores
Hi all, I understand the EEW, as explicitly encoded in the load/store instructions applies to the vector of indices for the indexed loads and stores. For instance we can load a vector "SEW=8,LMUL=1" u
Hi all, I understand the EEW, as explicitly encoded in the load/store instructions applies to the vector of indices for the indexed loads and stores. For instance we can load a vector "SEW=8,LMUL=1" u

By
Roger Ferrer Ibanez
· #383
·


EPI intrinsics reference and compiler updated to 0.8
Hi all, we have updated to version 0.8 of Vext our LLVMbased experimental compiler and the intrinsics reference. EPI builtins and examples: https://repo.hca.bsc.es/gitlab/rferrer/epibuiltinsref Co
Hi all, we have updated to version 0.8 of Vext our LLVMbased experimental compiler and the intrinsics reference. EPI builtins and examples: https://repo.hca.bsc.es/gitlab/rferrer/epibuiltinsref Co

By
Roger Ferrer Ibanez
· #24
·
