I haven’t seen any burning issues come by, and am still trying to clean up spec. So unless someone has agenda items, I’m canceling meeting tomorrow, Krste

I’m still working on spec cleanup and I don’ t have any major outstanding issues to discuss, so will cancel the TG meeting this week. Please bring up any burning issues on this mailing list, Krste

Date: 2021/03/26 Task Group: Vector Extension Chair: Krste Asanovic Vice-Chair: Roger Espasa Number of Attendees: ~10 Current issues on github: https://github.com/riscv/riscv-v-spec A short meeting di

We'll meet again in usual slot. The main discussion topic will be #545. Please read the issue thread on github. Summary: The proposal is to move vector AMOs from their current encoding to leave space

Date: 2021/03/19 Task Group: Vector Extension Chair: Krste Asanovic Vice-Chair: Roger Espasa Number of Attendees: ~16 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed #

There are a few issues to discuss, so we’ll meet in the regular time slot on the calendar, Krste

I'm cancelling meeting again, as I still have not been able to clean spec. I realize it will be more efficient for folks to wait for a clean version for a complete read through. Few issues are being r

I'm still working through spec cleanup. The list and github has been quiet, and I have no new issues to raise, so I suggest we cancel this meeting and push out for a week. Krste

Date: 2021/02/19 Task Group: Vector Extension Chair: Krste Asanovic Vice-Chair: Roger Espasa Number of Attendees: ~23 Current issues on github: https://github.com/riscv/riscv-v-spec # Next Meeting/Fre

We’ll meet today in usual slot, details on Google calendar Agenda is to discuss any issues found while reading over the v0.10 spec. List and GitHub has been quite quiet, so this might be a short meeti

If you check over the vector instruciton listing table It’s all the instructions in funct3=OPFVF with an F in the operand column. Most of these are missing. Krste

| in terms of overlap with that case — that case normally selects maximally sized AVL. the implied goals there are to make best use of vector register capacity and | throughput. l | i’m suggesting a c

| I agree with you. | I had suggested the mapping of 00000 to an implementation-defined value (chosen by the CPU architect). For some architectures, this may be 16, for others it may | be 32, or even

Replying to old thread to add rationale for current choice. | Does it get easier if the specification is just the immediate value plus one? No - this costs more gates on critical path. Mapping 00000 =

Date: 2021/02/05 Task Group: Vector Extension Chair: Krste Asanovic Vice-Chair: Roger Espasa Number of Attendees: ~16 Current issues on github: https://github.com/riscv/riscv-v-spec # Next Meeting It

We’ll meet tomorrow in usual slot per TG calendar. The agenda is to review any feedback on the 0.10 spec and then to proceed through any outstanding issues, Krste

Date: 2021/01/29 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~16 Current issues on github: https://github.com/riscv/riscv-v-spec # Meetings Meetings

I cut a v0.10 release after adding all the substantial pending updates. There is still a bunch of work to do before public review, but this is a convenient milestone for toolchain developers, Krste

I scheduled next vector TG meeting tomorrow in usual slot with usual zoom link on TG Google calendar. I hope to push out updated spec sometime before then, Krste

I was going to restart the vector TG meetings next week (Jan 29), and have a goal of having most pending updates added to the spec a few days before then. Krste