Date   
Zve should be a strict subset of V, use new option to relax VLEN By Guy Lemieux · #666 ·
Smaller embedded version of the Vector extension By Guy Lemieux · #656 ·
回复:Re: 回复:[RISC-V] [tech-vector-ext] RISC-V Vector Spec version 1.0-rc1-20210608 By Guy Lemieux · #650 ·
回复:Re: 回复:[RISC-V] [tech-vector-ext] RISC-V Vector Spec version 1.0-rc1-20210608 By Guy Lemieux · #647 ·
Smaller embedded version of the Vector extension By Guy Lemieux · #638 ·
Smaller embedded version of the Vector extension By Guy Lemieux · #635 ·
Smaller embedded version of the Vector extension By Guy Lemieux · #632 ·
Smaller embedded version of the Vector extension By Guy Lemieux · #618 ·
Smaller embedded version of the Vector extension By Guy Lemieux · #617 ·
Smaller embedded version of the Vector extension By Guy Lemieux · #612 ·
Check mask all ones / all zeros By Guy Lemieux · #605 ·
Check mask all ones / all zeros By Guy Lemieux · #603 ·
vector intrinsics for both RV32/RV64 By Guy Lemieux · #592 ·
Vector TG minutes for 2020/12/18 meeting By Guy Lemieux · #569 ·
Vector TG minutes for 2020/12/18 meeting By Guy Lemieux · #567 ·
Vector TG minutes for 2020/12/18 meeting By Guy Lemieux · #547 ·
vector strided stores when rs1=x0 By Guy Lemieux · #506 ·
[RISC-V] [tech] [RISC-V] [tech-*] STRATEGIC FEATURE COEXISTANCE was:([tech-fast-int] usefulness of PUSHINT/POPINT from [tech-code-size]) By Guy Lemieux · #493 ·
V extension groups analogue to the standard groups By Guy Lemieux · #367 ·
Vector Task Group minutes 2020/5/15 By Guy Lemieux · #182 ·
1 - 20 of 34