Sure. You could guarantee forward progress, e.g. by allowing no more than 10 successive "first fault" with VL=0, and requiring trap on element zero on the 11th. That check could be in hardware, or it

Yep, it's sufficient for the needs of while loop Vectorization. It is suboptimal for "SIMT on vector". For that you need a completion mask. and it is far too late to add that to the RISC-V vector spec

(I've been having email problems.)

For extended precision arithmetic, e.g. such as is often performed in cryptography, 2X widening multiply accumulate is the best that I have found. (And as far as I know other members of the cryptograp

RISC V needs CMOs, and hence a CMO Working Group EditNew Page All successful computer instruction sets have Cache Management Operations (CMOs). Several RISC-V systems have already defined implementati

Now I can add AsciiDoc and KramDoc artifacts to those HTML and PDF artifacts :-( [Andrew Waterman]: We have tagged version 0.9 on github, including HTML/PDF artifacts: https://github.com/riscv/riscv-v

Anecdote: One of my initial inspirations for working on dynamic out of order scheduling was to support incremental time pipeline vectors, both scatter/gather and stride. I.e. the P6 RS began as a vect

Oh, heck [*]: Callee saved registers of any form can have bad performance where there is a potential partial register issue. E.g. on an out of order machine with register renaming. Although even some