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Vector Task Group minutes 2020/12/04
8 Maks registers are quite needed in modern outer-vectorized loops. Also in graphic shaders. I would say 16 is overkill. Now, and I am not defending this, if we had to go this route, I would seriously
8 Maks registers are quite needed in modern outer-vectorized loops. Also in graphic shaders. I would say 16 is overkill. Now, and I am not defending this, if we had to go this route, I would seriously
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By
Roger Espasa
· #537
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change "raise illegal instruction" -> "reserved" for static encodings
Did you keep/add text encouraging implementations to indeed raise illegal on reserved encodings ? I went through the patch (rather quickly) and did not see it. Roger
Did you keep/add text encouraging implementations to indeed raise illegal on reserved encodings ? I went through the patch (rather quickly) and did not see it. Roger
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Roger Espasa
· #485
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[RISC-V] [tech-cmo] Fault-on-first should be allowed to return randomly on non-faults (also, running SIMT code on vector ISA)
So all the vleff use cases end up then using a vmpopc of some sort to determine the exit condition and never use the trimmed VL ? (other than, of course, to control within the while how many elements
So all the vleff use cases end up then using a vmpopc of some sort to determine the exit condition and never use the trimmed VL ? (other than, of course, to control within the while how many elements
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Roger Espasa
· #470
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[RISC-V] [tech-cmo] Fault-on-first should be allowed to return randomly on non-faults (also, running SIMT code on vector ISA)
We're all in agreement that if the spec says "pick where you stop" we'd all pick to trim to VL=3. I was under the impression this was not yet closed (in light of the "stop at cache misses" discussion)
We're all in agreement that if the spec says "pick where you stop" we'd all pick to trim to VL=3. I was under the impression this was not yet closed (in light of the "stop at cache misses" discussion)
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Roger Espasa
· #468
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[RISC-V] [tech-cmo] Fault-on-first should be allowed to return randomly on non-faults (also, running SIMT code on vector ISA)
Bill you said element 9, but did you mean element labeled "a" which is the 11th element in the vector? (I agree with that). However, I would NOT agree that a masked out element has been written, even
Bill you said element 9, but did you mean element labeled "a" which is the 11th element in the vector? (I agree with that). However, I would NOT agree that a masked out element has been written, even
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Roger Espasa
· #465
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[RISC-V] [tech-cmo] Fault-on-first should be allowed to return randomly on non-faults (also, running SIMT code on vector ISA)
Here's where the "implementation" cost comes in (at least in our implementation; others, of course, may have more clever ways of doing this) -> If you pick "vl=3", then the vstart and vltrim calculati
Here's where the "implementation" cost comes in (at least in our implementation; others, of course, may have more clever ways of doing this) -> If you pick "vl=3", then the vstart and vltrim calculati
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Roger Espasa
· #464
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[RISC-V] [tech-cmo] Fault-on-first should be allowed to return randomly on non-faults (also, running SIMT code on vector ISA)
Here's a question for the group: I did in as a picture... hopefully it will go through the mailing list:
Here's a question for the group: I did in as a picture... hopefully it will go through the mailing list:
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Roger Espasa
· #462
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Clarification on vid.v
Joseph, May I suggest you open a git issue here: https://github.com/riscv/riscv-v-spec/issues with these two questions? It will help better tracking and will ensure whatever the resolution is, it does
Joseph, May I suggest you open a git issue here: https://github.com/riscv/riscv-v-spec/issues with these two questions? It will help better tracking and will ensure whatever the resolution is, it does
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Roger Espasa
· #446
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Vector Task Group minutes 2020/5/15
You're absolutely right. Thanks for the correction.
You're absolutely right. Thanks for the correction.
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Roger Espasa
· #187
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Vector Task Group minutes 2020/5/15
I was trying to summarize/compare the different proposals. I talked to Grigoris and I think this is a correct summary: v08 v09 Grigoris LMUL=1 SLEN=VLEN SLEN does not matter SLEN does not matter SLEN
I was trying to summarize/compare the different proposals. I talked to Grigoris and I think this is a correct summary: v08 v09 Grigoris LMUL=1 SLEN=VLEN SLEN does not matter SLEN does not matter SLEN
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By
Roger Espasa
· #185
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Effective element width encoding in vector load/stores
I really like the fact that this solves indexed. It's a pretty good proposal overall, and I think it beats adding "quad" extension and then a debate over "quad-with-add", "quad-with-sub", "quad-with-<
I really like the fact that this solves indexed. It's a pretty good proposal overall, and I think it beats adding "quad" extension and then a debate over "quad-with-add", "quad-with-sub", "quad-with-<
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Roger Espasa
· #95
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A couple of questions about the vector spec
On #2, it would require finding a 2 bit field in the vector load format to encode "no-scaling/2/4/8". Not trivial within the 32b format. On Wed, Mar 11, 2020 at 1:30 AM Nagendra Gulur <nagendra.gd@gma
On #2, it would require finding a 2 bit field in the vector load format to encode "no-scaling/2/4/8". Not trivial within the 32b format. On Wed, Mar 11, 2020 at 1:30 AM Nagendra Gulur <nagendra.gd@gma
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Roger Espasa
· #70
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Vector Indexed Loads - Partial Return?
Not really challenge :-) But it's the only option if you can't / don't want to add a "vstart" equivalent (because you don't want to save/restore it...) @Nagendra: note that the spec does require the m
Not really challenge :-) But it's the only option if you can't / don't want to add a "vstart" equivalent (because you don't want to save/restore it...) @Nagendra: note that the spec does require the m
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Roger Espasa
· #68
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