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RISC-V Vector Extension post-public review updates
Almost all vector instructions already have to check their vector operands to make sure the register numbers are compatible with (dynamic) LMUL. This is further complicated in, e.g., the case of mixed
Almost all vector instructions already have to check their vector operands to make sure the register numbers are compatible with (dynamic) LMUL. This is further complicated in, e.g., the case of mixed
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By
Nick Knight
· #731
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RISC-V Vector Extension post-public review updates
https://godbolt.org/z/qj6WzYc76
https://godbolt.org/z/qj6WzYc76
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By
Nick Knight
· #723
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Configuring qemu for Vector Extension
V-extension version 1.0 hasn't been frozen yet. Its second release candidate was posted just yesterday: https://github.com/riscv/riscv-v-spec/releases/tag/v1.0-rc2 I wouldn't expect toolchain support
V-extension version 1.0 hasn't been frozen yet. Its second release candidate was posted just yesterday: https://github.com/riscv/riscv-v-spec/releases/tag/v1.0-rc2 I wouldn't expect toolchain support
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By
Nick Knight
· #688
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Smaller embedded version of the Vector extension
Hi Tony, All of the vector permutation instructions can be simulated using the memory system. For example, vslide can be simulated by storing the vector register and loading it at an offset; vrgather
Hi Tony, All of the vector permutation instructions can be simulated using the memory system. For example, vslide can be simulated by storing the vector register and loading it at an offset; vrgather
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By
Nick Knight
· #628
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FYI: ARM vs. RISC-V vector extension conmparison
I guess the publicity doesn't hurt, but I do wish the author had considered our developments here (at riscv/riscv-v-spec). His material appears to derive from Patterson-Waterman's 2017 book (and sigar
I guess the publicity doesn't hurt, but I do wish the author had considered our developments here (at riscv/riscv-v-spec). His material appears to derive from Patterson-Waterman's 2017 book (and sigar
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By
Nick Knight
· #590
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vector strided stores when rs1=x0
I understand now. I'm on board iff the memory consistency model experts assent.
I understand now. I'm on board iff the memory consistency model experts assent.
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By
Nick Knight
· #511
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vector strided stores when rs1=x0
Sorry, slightly off topic, but what was the rationale for I guess I'm thinking about the possibility of a toolchain relaxing `li, x1, 0; inst x1` into `inst x0`.
Sorry, slightly off topic, but what was the rationale for I guess I'm thinking about the possibility of a toolchain relaxing `li, x1, 0; inst x1` into `inst x0`.
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By
Nick Knight
· #509
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Sparse Matrix-Vector Multiply (again) and Bit-Vector Compression
Hi Dawei, Unfortunately the V-extension does not currently feature block-matrix multiplication instructions, including the bit-masked versions that you're describing. Some of these operations are inte
Hi Dawei, Unfortunately the V-extension does not currently feature block-matrix multiplication instructions, including the bit-masked versions that you're describing. Some of these operations are inte
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By
Nick Knight
· #478
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Proposing more portable vector cod
Hi Joseph, Thanks for the clarification. The wording in the spec is admittedly vague: "LMUL can have integer values 1,2,4,8.", etc. My understanding of the intent is that all implementations must supp
Hi Joseph, Thanks for the clarification. The wording in the spec is admittedly vague: "LMUL can have integer values 1,2,4,8.", etc. My understanding of the intent is that all implementations must supp
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By
Nick Knight
· #439
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Proposing more portable vector cod
Sorry, in case it wasn't clear: typo it's not too much of a burden.
Sorry, in case it wasn't clear: typo it's not too much of a burden.
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By
Nick Knight
· #437
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Proposing more portable vector cod
Hi Joseph, Thanks for your comments. I apologize, but I don't fully understand your proposal, or the problem it solves. To help explain my confusion, here are two thoughts. The supported LMUL (and EMU
Hi Joseph, Thanks for your comments. I apologize, but I don't fully understand your proposal, or the problem it solves. To help explain my confusion, here are two thoughts. The supported LMUL (and EMU
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By
Nick Knight
· #436
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Please check new Google calendar for new vector TG meeting link
Hi Cohen, I can see the calendar here: https://lists.riscv.org/g/tech-vector-ext/calendar Unfortunately, due to a conflict I can only rarely attend the TG meeting. Best, Nick
Hi Cohen, I can see the calendar here: https://lists.riscv.org/g/tech-vector-ext/calendar Unfortunately, due to a conflict I can only rarely attend the TG meeting. Best, Nick
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By
Nick Knight
· #430
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Mask Register Value Mapping
The existing draft used the notation v0.mask[i] in dozens of places to denote subscripting of a mask vector (bit granularity). I opted to use the existing notation uniformly, rather than switch to Dav
The existing draft used the notation v0.mask[i] in dozens of places to denote subscripting of a mask vector (bit granularity). I opted to use the existing notation uniformly, rather than switch to Dav
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By
Nick Knight
· #427
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Mask Register Value Mapping
I believe so: I am not aware of any proposals to reintroduce MLEN.
I believe so: I am not aware of any proposals to reintroduce MLEN.
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By
Nick Knight
· #423
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Mask Register Value Mapping
Hi Cohen, I think the "LSB references" are carryovers from pre-0.9 versions, when MLEN > 1 was possible. I can put together a PR to fix this later tonight, unless someone else gets to it sooner. Best,
Hi Cohen, I think the "LSB references" are carryovers from pre-0.9 versions, when MLEN > 1 was possible. I can put together a PR to fix this later tonight, unless someone else gets to it sooner. Best,
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By
Nick Knight
· #421
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V-ext white paper?
Hi team, Do we have a plan to write a V-extension white paper? Is there any interest? I'm thinking along the lines of ARM's SVE paper in IEEE Micro '17. I don't know if this is feasible or appropriate
Hi team, Do we have a plan to write a V-extension white paper? Is there any interest? I'm thinking along the lines of ARM's SVE paper in IEEE Micro '17. I don't know if this is feasible or appropriate
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By
Nick Knight
· #416
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Signed v Unsigned Immediate: vsaddu.vi
Hi Cohen, Thanks for your careful reading. Hopefully this edit clarifies some of the ambiguity: https://github.com/riscv/riscv-v-spec/pull/565 Best, Nick Knight
Hi Cohen, Thanks for your careful reading. Hopefully this edit clarifies some of the ambiguity: https://github.com/riscv/riscv-v-spec/pull/565 Best, Nick Knight
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By
Nick Knight
· #382
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Fixed Point (Chapter 13): Clarification Request
Hi Coheen, Thanks for the discussion on the fixed-point vector instructions. Most of Chapter 13 predates my involvement with the Task Group, but I think I am able to address one of your comments: Here
Hi Coheen, Thanks for the discussion on the fixed-point vector instructions. Most of Chapter 13 predates my involvement with the Task Group, but I think I am able to address one of your comments: Here
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By
Nick Knight
· #328
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Sparse Matrix-Vector Multiply (again) and Bit-Vector Compression
I believe that the (rough) idea I sketched earlier in this thread (May 8) still works with the latest version of the spec --- please correct me if I'm wrong --- what I called "sketchy type-punning" (o
I believe that the (rough) idea I sketched earlier in this thread (May 8) still works with the latest version of the spec --- please correct me if I'm wrong --- what I called "sketchy type-punning" (o
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By
Nick Knight
· #260
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Vector-scalar instructions
Hi Rich, The reduction operations retain the `.vs` suffix: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#16-vector-reduction-operations Best, Nick Knight
Hi Rich, The reduction operations retain the `.vs` suffix: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#16-vector-reduction-operations Best, Nick Knight
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By
Nick Knight
· #247
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