tech-vector-ext@lists.riscv.org

Seeking inputs for evaluating vector ABI design

I would like to emphasize Zalman Stern's point about trading off hardware economy for dynamic software optimization, in the context of a larger comment about optimizing compiled code for RISC-V. The s

By ghost · #813 ·

[RISC-V] [tech-unprivileged] [RISC-V] [tech-vector-ext] FP Trapped exceptions needed for portability

Along with this, I'd suggest considering an extension that consists of just one instruction: trap if (FP flags & mask in instruction) is non-zero. I'm not a hardware designer, but it seems to me that

By ghost · #775 ·

RISC-V Vector Extension post-public review updates

I agree that #1 is the least unfortunate of the alternatives, but I want to raise a flag because I think there are larger considerations. AFAIK, the vector extensions are unique among proposed non-pri

By ghost · #729 ·

Zve should be a strict subset of V, use new option to relax VLEN

FYI, I'm working with Elisa Sawyer and others on a style and content guide for extension proposals, mostly based on the excellent bitmanip v1.0.0-rc1 draft. That draft includes a table like the one yo

By ghost · #671 ·

New member request for participation info

Hello, I've just joined the RISC-V technical community and the V Extension Task group. I have very substantial experience in careful technical documentation (I wrote the RFCs for gzip and DEFLATE, and

By ghost · #564 ·