Hi Mick, This is what I do for 32-bit RISC-V Vector on ubuntu1804, admittedly it took me a long time to find a combination that worked and I had help to get the correct switches: Risc-V Vector 32-bit

It might be worth updating sections: 7.5 Vector Strided Instructions 7.6 Vector Indexed Instructions with the address calculations to specify the stride offsets and indexs and byte sized, rather than

Hi Mick, I use the RISC-V Vector QEMU branch from SiFive (for 32-bit, don’t know about 64-bit support though): https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v7-fix Also, there may be a later ve

Software should still work with VLEN>=64 if written correctly, as it should be VLEN agnostic. Maybe it should be a recommendation that VLEN>=128, with a minimum of 64 for app processors? Lower perform

Hi Bruce, Do you mean vrgather instead of vslide? I use vrgather_vx_* and vslidedown to perform a vector element rotate (and other things), see: https://github.com/riscv/riscv-v-spec/issues/671#issuec

Thanks, I must have missed this bit: "4.5. Mapping with LMUL > 1 and ELEN > VLEN If vector registers are grouped to support larger SEW, with ELEN > VLEN, the vector registers in the group are concaten

Hi Bruce, “I an not a fan of the vslide instructions. It seems they expose the size of the vector registers in a very unfortunate way. In particular they break down if VLEN=1. Most code would be bette

So, (on a 32x 32-bit vector register machine) the widening and narrowing instructions can use 64-bit elements (for destination and source respectively), but not any of other instructions, correct? Not

Having 32x 32 bit registers with LMUL=4, giving 8x 128 bits - does this allow for 64-bit elements? I don't think it does, but it’s not clear in the spec. I use 64-bit elements for “wide” and “quad” ac

Hi all, I’m still new to RISC-V and the Vector extensions, so forgive me if I’ve missed something, the following have been fixed or noted before. Also, am I sending this to the correct group for GCC R

#defines

Hi Vector Team, I’m new to RISC-V and the Vector extensions, so forgive me if I’ve missed something. I have searched the specs, emails and git hub issues, but not found anything on this: While writing