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official v0.8 release of vector spec reference simulator
Simon Davidmann Imperas
We have just released an update of our free riscvOVPsim reference simulator version: 20191217.0 and put it on the https://github.com/riscv/riscv-ovpsim.
riscvOVPsim supports the full latest Vector instruction v0.8 release and is available now.
Our policy is to update our free reference simulator as soon as the vector specification updates - normally 2-3 days after the vector spec is updated. [We need to do this as our customers who are creating silicon need up-to-the-minute reference model for verification.]
riscvOVPsim is a complete envelope model of the full RISC-V 32/64 specification and is configured by command line options.
An example from its documentation for the vectors (last months spec changes) is:
Stable 0.8 draft of November 18 2019, with these changes compared to version 0.8-draft-20191117:Version 0.8-draft-20191117
Stable0.8 draft of November 17 2019, with these changes compared to version 0.8-draft-20191004:Version 0.8-draft-20191004
Stable 0.8 draft of October 4 2019, with these changes compared to version 0.8-draft-20190906:etc...
For full documentation, please clone the repo or browse the simulator doc: https://github.com/riscv/riscv-ovpsim/blob/master/doc/OVP_Model_Specific_Information_riscv_RV64GCV.pdf
thanks for your interest
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