Vector-scalar instructions


Richard Newell
 

Sorry for what may be a question with an answer that may be obvious to those that have been at all the meetings:

 

Have the vector-scalar instructions (.vs) been eliminated from the vector extensions?  By this, I mean where the scalar comes from vector element zero.  I only see things like .vx for the arithmetic instructions, where the scalar comes from any of the general-purpose “x” (or alternatively, the floating-point) registers in my reading of the latest version of the specification.

 

Rich

 

G. Richard Newell
Associate Technical Fellow

FPGA Business Unit
3870 N. First Street
San Jose, CA 95134

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PGP Fingerprints:
(2009 DSA-1024, ELG-4096) B751 FC13 8B4E 49DA 2270 35A2 20E4 E66A D0D0 2E34

(2016 SSA-4096, RSA-4096) 65F5 CCD6 23B3 BD3D CEDE AB58 171F F4DE E7D0 3ECA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 


Nick Knight
 

Hi Rich,


Best,
Nick Knight


On Wed, Jul 1, 2020 at 10:23 AM Richard Newell via lists.riscv.org <richard.newell=microchip.com@...> wrote:

Sorry for what may be a question with an answer that may be obvious to those that have been at all the meetings:

 

Have the vector-scalar instructions (.vs) been eliminated from the vector extensions?  By this, I mean where the scalar comes from vector element zero.  I only see things like .vx for the arithmetic instructions, where the scalar comes from any of the general-purpose “x” (or alternatively, the floating-point) registers in my reading of the latest version of the specification.

 

Rich

 

G. Richard Newell
Associate Technical Fellow

FPGA Business Unit
3870 N. First Street
San Jose, CA 95134

+1 (408) 643-6146 (office)
+1 (408) 882-4785 (mobile)

+1 (925) 478-7258 (Skype)
richard.newell@...

PGP Fingerprints:
(2009 DSA-1024, ELG-4096) B751 FC13 8B4E 49DA 2270 35A2 20E4 E66A D0D0 2E34

(2016 SSA-4096, RSA-4096) 65F5 CCD6 23B3 BD3D CEDE AB58 171F F4DE E7D0 3ECA