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an interesting paper
i was made aware of this paper. risc-v vectors are mentioned.
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one of the key conclusions are (from the abstract)
Our experiments show that VLA code reaches about 90% of the performance of vector length specific code, i.e. a 10% overhead is inferred due to global predication of instructions. Furthermore, we show that code performance is not increasing proportionally with increasing vector lengths due to the higher memory demands.
my experience is just the opposite. (based on memory system design)
i am curious to hear other opinions
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They mention RISC-V vectors in the intro, but on a quick scan, the
results are very ARM-specific, with no real implication for RISC-V
vectors. They're pointing out a problem with ARM SVE where all
elements are executed regardless of vector length due to SVE using
predication to implement vector length.
Krste
| one of the key conclusions are (from the abstract)
| Our experiments show that VLA code reaches about 90% of the performance of
| vector length specific code, i.e. a 10% overhead is inferred due to global
| predication of instructions. Furthermore, we show that code performance is not
| increasing proportionally with increasing vector lengths due to the higher
| memory demands.
| my experience is just the opposite. (based on memory system design)
| i am curious to hear other opinions
| WARNING / LEGAL TEXT: This message is intended only for the use of the
| individual or entity to which it is addressed and may contain information
| which is privileged, confidential, proprietary, or exempt from disclosure
| under applicable law. If you are not the intended recipient or the person
| responsible for delivering the message to the intended recipient, you are
| strictly prohibited from disclosing, distributing, copying, or in any way
| using this message. If you have received this communication in error, please
| notify the sender and destroy and delete any copies you may have received.
| http://www.bsc.es/disclaimer
|
| x[DELETED ATTACHMENT PohlAPPMM19.pdf, PDF]
results are very ARM-specific, with no real implication for RISC-V
vectors. They're pointing out a problem with ARM SVE where all
elements are executed regardless of vector length due to SVE using
predication to implement vector length.
Krste
| i was made aware of this paper. risc-v vectors are mentioned.On Mon, 14 Sep 2020 08:46:05 -0500, "swallach" <steven.wallach@...> said:
| one of the key conclusions are (from the abstract)
| Our experiments show that VLA code reaches about 90% of the performance of
| vector length specific code, i.e. a 10% overhead is inferred due to global
| predication of instructions. Furthermore, we show that code performance is not
| increasing proportionally with increasing vector lengths due to the higher
| memory demands.
| my experience is just the opposite. (based on memory system design)
| i am curious to hear other opinions
| WARNING / LEGAL TEXT: This message is intended only for the use of the
| individual or entity to which it is addressed and may contain information
| which is privileged, confidential, proprietary, or exempt from disclosure
| under applicable law. If you are not the intended recipient or the person
| responsible for delivering the message to the intended recipient, you are
| strictly prohibited from disclosing, distributing, copying, or in any way
| using this message. If you have received this communication in error, please
| notify the sender and destroy and delete any copies you may have received.
| http://www.bsc.es/disclaimer
|
| x[DELETED ATTACHMENT PohlAPPMM19.pdf, PDF]
i agree with your comment
i got this paper from someone who applied their assessment to risc-v vectors
http://bsc.es/disclaimer
i got this paper from someone who applied their assessment to risc-v vectors
On Sep 14, 2020, at 10:47 AM, krste@... wrote:
They mention RISC-V vectors in the intro, but on a quick scan, the
results are very ARM-specific, with no real implication for RISC-V
vectors. They're pointing out a problem with ARM SVE where all
elements are executed regardless of vector length due to SVE using
predication to implement vector length.
Krste| i was made aware of this paper. risc-v vectors are mentioned.On Mon, 14 Sep 2020 08:46:05 -0500, "swallach" <steven.wallach@...> said:
| one of the key conclusions are (from the abstract)
| Our experiments show that VLA code reaches about 90% of the performance of
| vector length specific code, i.e. a 10% overhead is inferred due to global
| predication of instructions. Furthermore, we show that code performance is not
| increasing proportionally with increasing vector lengths due to the higher
| memory demands.
| my experience is just the opposite. (based on memory system design)
| i am curious to hear other opinions
| WARNING / LEGAL TEXT: This message is intended only for the use of the
| individual or entity to which it is addressed and may contain information
| which is privileged, confidential, proprietary, or exempt from disclosure
| under applicable law. If you are not the intended recipient or the person
| responsible for delivering the message to the intended recipient, you are
| strictly prohibited from disclosing, distributing, copying, or in any way
| using this message. If you have received this communication in error, please
| notify the sender and destroy and delete any copies you may have received.
| http://www.bsc.es/disclaimer
|
| x[DELETED ATTACHMENT PohlAPPMM19.pdf, PDF]
http://bsc.es/disclaimer