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Clarification on vid.v

Joseph Rahmeh <joseph.rahmeh@...>
 

 

Should vid.v raise an illegal instruction exception when masked and when the destination group overlaps v0 ?

Should vid.v raise an illegal instruction exception when vstart > 0 ?
Roger Espasa
 

Joseph,

May I suggest you open a git issue here: https://github.com/riscv/riscv-v-spec/issues with these two questions? It will help better tracking and will ensure whatever the resolution is, it does make it into the spec.

roger.

On Sat, Oct 3, 2020 at 8:09 PM Joseph Rahmeh <joseph.rahmeh@...> wrote:

 

Should vid.v raise an illegal instruction exception when masked and when the destination group overlaps v0 ?

Should vid.v raise an illegal instruction exception when vstart > 0 ?
Joseph Rahmeh <joseph.rahmeh@...>
 

Done.  Thanks Roger.

 

From: Roger Espasa <roger.espasa@...>
Date: Sunday, October 4, 2020 at 12:49 PM
To: Joseph Rahmeh <Joseph.Rahmeh@...>
Cc: "tech-vector-ext@..." <tech-vector-ext@...>, Robert Golla <Robert.Golla@...>, Cohen Steed <Cohen.Steed@...>, Christopher Olson <Christopher.Olson@...>, Matthew Smittle <Matthew.Smittle@...>
Subject: Re: [RISC-V] [tech-vector-ext] Clarification on vid.v

 

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Joseph,

 

May I suggest you open a git issue here: https://github.com/riscv/riscv-v-spec/issues with these two questions? It will help better tracking and will ensure whatever the resolution is, it does make it into the spec.

 

roger.

 

On Sat, Oct 3, 2020 at 8:09 PM Joseph Rahmeh <joseph.rahmeh@...> wrote:

 

Should vid.v raise an illegal instruction exception when masked and when the destination group overlaps v0 ?

Should vid.v raise an illegal instruction exception when vstart > 0 ?

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