GCC RISC-V Vector Intrinsic Instructions and #defines missing #defines


Tony Cole
 

Hi all,

 

I’m still new to RISC-V and the Vector extensions, so forgive me if I’ve missed something, the following have been fixed or noted before.

 

Also, am I sending this to the correct group for GCC RISC-V Vector Intrinsics? If not, who and how should I inform?

 

 

 

I’m currently using: riscv32-unknown-elf-gcc (GCC) 10.1.0    (…/10.1.0–rvv-intrinsic-patch/bin/ riscv32-unknown-elf-gcc – version)

 

 

These (and probably others) don’t exist in the GCC compiler RISCV Vector intrinsics (the m8 versions):

 

        vint32m1_t vwredsum_vs_i16m8_i32m1 (vint32m1_t dst, vint16m8_t vector, vint32m1_t scalar, size_t vl);

        vint64m1_t vwredsum_vs_i32m8_i64m1 (vint64m1_t dst, vint32m8_t vector, vint64m1_t scalar, size_t vl);

 

They are listed in here: https://github.com/riscv/rvv-intrinsic-doc/blob/master/intrinsic_funcs/09_vector_reduction_functions.md

 

 

So, I’ve had to temporally change to (the m4 versions):

 

        vint32m1_t vwredsum_vs_i16m4_i32m1 (vint32m1_t dst, vint16m4_t vector, vint32m1_t scalar, size_t vl);
        vint64m1_t vwredsum_vs_i32m4_i64m1 (vint64m1_t dst, vint32m4_t vector, vint64m1_t scalar, size_t vl);

 

to get it to compile and work.

 

This may have already been fixed? Please let me know.

 

 

 

Also,

 

I was expecting to find some #defines for the rounding modes in riscv-vector.h, something like:

 

/* Vector Fixed-Point Rounding Mode Register vxrm settings

   Use with vwrite_csr(RVV_VXRM, RVV_VXRM_XXX) */

 

#define RVV_VXRM_RNU  (0) /* Round-to-nearest-up (add 0.5 LSB) */

#define RVV_VXRM_RNE  (1) /* Round-to-nearest-even */

#define RVV_VXRM_RDN  (2) /* Round-down (truncate) */

#define RVV_VXRM_ROD  (3) /* Round-to-add (OR bits into LSB, aka "jam") */

 

Tony Cole

CPU Consultant I RISC-V Cores, Bristol

E-mail: Tony.Cole@...

Company: Huawei technologies R&D (UK) Ltd I Address: 290 Park Avenue, Aztec West, Almondsbury, Bristol, Avon, BS32 4SY, UK      

 

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Jim Wilson
 

On Fri, Apr 9, 2021 at 3:40 PM Tony Cole via lists.riscv.org <tony.cole=huawei.com@...> wrote:

I’m still new to RISC-V and the Vector extensions, so forgive me if I’ve missed something, the following have been fixed or noted before.

Also, am I sending this to the correct group for GCC RISC-V Vector Intrinsics? If not, who and how should I inform?


I would suggest filing an issue in the riscv/riscv-gnu-toolchain github tree.  Put something like vector or rvv in the issue title to make it clear it is a vector related issue.  The gcc support is not being actively worked on at the moment.  LLVM is the current focus for all vector compiler support.  Eventually someone may start working on the gcc vector support again.  Meanwhile, bugs filed against the gcc vector support may or may not be fixed.

Jim


Kito Cheng
 

Hi Tony:

Could you create issues on github to track that?
https://github.com/riscv/riscv-gcc

Thanks :)

On Sat, Apr 10, 2021 at 9:14 AM Jim Wilson <jimw@sifive.com> wrote:

On Fri, Apr 9, 2021 at 3:40 PM Tony Cole via lists.riscv.org <tony.cole=huawei.com@lists.riscv.org> wrote:

I’m still new to RISC-V and the Vector extensions, so forgive me if I’ve missed something, the following have been fixed or noted before.

Also, am I sending this to the correct group for GCC RISC-V Vector Intrinsics? If not, who and how should I inform?

I would suggest filing an issue in the riscv/riscv-gnu-toolchain github tree. Put something like vector or rvv in the issue title to make it clear it is a vector related issue. The gcc support is not being actively worked on at the moment. LLVM is the current focus for all vector compiler support. Eventually someone may start working on the gcc vector support again. Meanwhile, bugs filed against the gcc vector support may or may not be fixed.

Jim