[EXT] Re: [RISC-V] [tech-vector-ext] FP Trapped exceptions needed for portability
Completely agree. Was very happy RISC-V did not include FPU exceptions.
From: tech-vector-ext@... <tech-vector-ext@...> On Behalf Of Andrew Waterman via lists.riscv.org
Sent: Friday, December 17, 2021 1:48 PM
To: Ken Dockser <kad@...>
Cc: tech-alternate-fp@...; tech-unprivileged@...; tech-vector-ext@...
Subject: [EXT] Re: [RISC-V] [tech-vector-ext] FP Trapped exceptions needed for portability
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Defining a standard extension that provides precise traps on FP exceptions seems like a reasonable thing to do, if only to facilitate the use case you mention in a standard way. The strategy would presumably be to add another five bits to the fcsr that indicate which exceptions will raise traps.
But I’ll also briefly remark that not requiring traps on FP exceptions has been a godsend for implementing high-performance in-order cores, where data-dependent traps would preclude early retirement and deferred execution of these instructions. So there’s good reason never to make such an extension mandatory, even in the RVA profiles.
On Fri, Dec 17, 2021 at 11:31 AM Ken Dockser <kad@...> wrote:
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