chapter 7.8. Vector Load/Store Segment Instructions
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As far as I understand, there is no separate field for decoding a segment instruction other than NF. Therefore, those instructions are considered segmented if NFIELDS > 1 (nf != 0).
01.02.2022, 10:54, "Alexander Podoplelov" <alexander.podoplelov@...>:
I have a question about vector segment load and stores.
In table 14 we have NFIELDS from 1 to 8.
In paragraphes 7.8.1-3 we have format like
vlseg<nf>e<eew>.v vd, (rs1), vm
vsseg<nf>e<eew>.v vs3, (rs1), vm
From specification it is not clear for me
Is it possible to have instruction like vlseg1e8.v
vd, (rs1), vm
This question is about all vector segment load and stores.
Right now assembly do not know opcodes for these instructions.
Despite of there is no any sense of using vlseg1e8.v
vd, (rs1), vm (please, correct me if I wrong) I suppose it is need
to be noted somewhere about supporting / not supporting these
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