LLVM with RVV intrinsic support
We would like to announce that the RISC-V V-extension v0.10 has been implemented in LLVM and the work has been committed upstream.
Barcelona Supercomputing Center (BSC), Codeplay Software, and SiFive have worked together to implement the RVV C API intrinsics for the V-extension and have implemented the foundation of CodeGen for Vector Length Specific (VLS) and Vector Length Agnostic (VLA) autovectorization for RISC-V.
What we have committed to LLVM upstream:
* Support for the v0.10 V-extension specification
* Support for the RVV C intrinsics in https://github.com/riscv/rvv-intrinsic-doc/tree/v0.10
* Implement the draft vector calling convention in https://github.com/riscv/riscv-elf-psabi-doc/pull/171
* C intrinsics for Zvlsseg implementation is under discussion:
* What type we should use for fp16 is under discussion:
RISC-V RVV example:
clang --target=riscv64-unknown-elf -march=rv64gcv0p10 -menable-experimental-extensions rvv_saxpy.c -o rvv_saxpy.elf
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Congratulations, and thank you!!
On Fri, May 14, 2021, 05:21 Kai Wang, <kai.wang@...> wrote: