official v0.8 release of vector spec reference simulator

Simon Davidmann Imperas

Krste, Roger

We have just released an update of our free riscvOVPsim reference simulator version: 20191217.0  and put it on the

riscvOVPsim supports the full latest Vector instruction v0.8 release and is available now.

Our policy is to update our free reference simulator as soon as the vector specification updates - normally 2-3 days after the vector spec is updated. [We need to do this as our customers who are creating silicon need up-to-the-minute reference model for verification.]

riscvOVPsim is a complete envelope model of the full RISC-V 32/64 specification and is configured by command line options.

An example from its documentation for the vectors (last months spec changes) is:
Version 0.8
Stable 0.8 official release (commit 9a65519), with these changes compared to version 0.8-draft-20191118:
- vector context status in mstatus register is now implemented;
- whole register load and store operations have been restricted to a single register only;
- whole register move operations have been restricted to aligned groups of 1, 2, 4 or 8 registers only.
Version 0.8-draft-20191118
Stable 0.8 draft of November 18 2019, with these changes compared to version 0.8-draft-20191117:
- vsetvl/vsetvli with rd!=zero and rs1=zero sets vl to the maximum vector length.
Version 0.8-draft-20191117
Stable0.8 draft of November 17 2019, with these changes compared to version 0.8-draft-20191004:
- indexed load/store instructions zero-extend offsets (previously, they were sign-extended);
- vslide1up/vslide1down instructions sign-extend XLEN values to SEW length (previously, they
were zero-extended);
- vadc/vsbc instruction encodings require vm=0 (previously, they required vm=1);
- vmadc/vmsbc instruction encodings allow both vm=0, implying carry input is used, and vm=1,
implying carry input is zero (previously, only vm=1 was permitted, implying carry input is used);
- vaaddu.vv, vaaddu.vx, vasubu.vv and vasubu.vx instructions added;
- vaadd.vv and vaadd.vx, instruction encodings changed;
- instruction removed;
- all widening saturating scaled multiply-add instructions removed;
- vqmaccu.vv, vqmaccu.vx, vqmacc.vv, vqmacc.vx, vqmacc.vx, vqmaccsu.vx and vqmaccus.vx in-
structions added;
- CSR vlenb added (vector register length in bytes);
- load/store whole register instructions added;
- whole register move instructions added.
Version 0.8-draft-20191004
Stable 0.8 draft of October 4 2019, with these changes compared to version 0.8-draft-20190906:
- vwsmaccsu and vwsmaccus instruction encodings exchanged.
For full documentation, please clone the repo or browse the simulator doc:

thanks for your interest

Simon Davidmann
Imperas Software