Hi all, A reminder that the next open meeting to discuss on the RISC-V V C Intrinsic API v1.0 is going to be held later on 2023/05/15 7AM (GMT -7) / 10PM (GMT +8). The agenda can be found in the secon

Hi all, A reminder that the next open meeting to discuss on the RISC-V V C Intrinsic API v1.0 is going to be held later on 2023/04/17 6AM (GMT -7) / 11PM (GMT +8). The agenda can be found in the secon

I’m somewhat unclear on the intended semantics for the vector fixed-point averaging add/sub instructions. The description is “The averaging add and subtract instructions right shift the result by one

The meeting minutes in added in the note. You can also find it under riscv-admin/rvv-intrinsics.

Hi all, A reminder that the next open meeting to discuss on the RISC-V V C Intrinsic API v1.0 is going to be held later on 2023/03/20 6AM (GMT -7) / 11PM (GMT +8). The agenda can be found in the secon

Hi all, I’m looking at sections 11.10, 11.12, and 11.14 in the V extension spec, version 1.0. The order of operands vs1/rs1 and vs2 appears to be reversed in the assembler for the multiply-add instruc

Hi all, A reminder that the next open meeting to discuss on the RISC-V V C Intrinsic API v1.0 is going to be held later on 2022/02/23 6AM (GMT -7) / 11PM (GMT +8). The agenda can be found in the secon

The meeting minutes in added in the note. You can also find it under riscv-admin/rvv-intrinsics.

Hi all, A reminder that the next open meeting to discuss on the RISC-V V C Intrinsic API v1.0 release is going to be held later on 2022/02/02 6AM (GMT -7) / 11PM (GMT +8). The agenda can be found in t

We are delighted to announce the start of the public review period for the following proposed standard extensions to the RISC-V ISA: Zvfh Zvfhmin The review period begins today, January 24, 2023 and e

Hi all, A reminder that the next open meeting to discuss on the RISC-V V C Intrinsic API v1.0 release is going to be held on 2023/01/05 6AM (GMT -7) / 11PM (GMT +8). The agenda can be found in the sec

Hi Krste, At the summit, you mentioned that the V opcode space would be extended by using P opcodes since an implementation would not have both P and V. Andes vector cores do have the P extension and

The meeting minutes in added in the note. You can also find it under riscv-admin/rvv-intrinsics.

Hi all, A reminder that the next open meeting to discuss on the RISC-V V C Intrinsic API v1.0 release is going to be held on 2022/11/28 6AM (GMT -7) / 11PM (GMT +8). For folks in Asia, be noted that t

A few issues have been identified in corners of the vector spec. The first change was an error of omission in not catching some cases of source and destination register overlap that can not be sensibl

The second fix is just a clarification of a missing case in the spec: "vsetvl[i] with rd=rs1=x0 is reserved if vill was 1 beforehand." The "vsetvl[i] x0, x0" form is defined in terms of whether VLMAX

Hi all, A reminder that the next open meeting to discuss on the RISC-V V C Intrinsic API v1.0 release is going to be held on 2022/10/31 7AM (GMT -7) / 10PM (GMT +8). The agenda can be found in the sec

From: Krste Asanovic via lists.riscv.org Sent: Thursday, October 6, 2022 12:42 PM We can delay, but not prevent, the need to have greater than 32b instructions. I worked on another RISC ISA for 25+ ye

These RISC-V vector extensions to handle IEEE FP16 were defined prior to ratification of the vector specification, but were left out of RVV 1.0 as they were not to be included in the base V extension.

Hi all, A reminder that an open meeting to draft the RISC-V V C Intrinsic API v1.0 release is going to be held later on 2022/10/03 7AM (GMT -7) / 10PM (GMT +8). Slide has been posted and agenda is in