
[RISCV] [tech*] STRATEGIC FEATURE COEXISTANCE was:([techfastint] usefulness of PUSHINT/POPINT from [techcodesize]) 4 messages
These are all important considerations. However, what they have in common when considering Allen's question: is that they are all tactical considerations are in the context of our current framework of
These are all important considerations. However, what they have in common when considering Allen's question: is that they are all tactical considerations are in the context of our current framework of

By
David Horner
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Sparse MatrixVector Multiply (again) and BitVector Compression 13 messages
I am now investigating how to efficiently implement sparse matrix X (dense) vector multiplications (spMV) using RISCV vectors using bitvector format of compressing the sparse matrix. The inner loop o
I am now investigating how to efficiently implement sparse matrix X (dense) vector multiplications (spMV) using RISCV vectors using bitvector format of compressing the sparse matrix. The inner loop o

By
Nagendra Gulur
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[RISCV] [tech] [RISCV] [tech*] STRATEGIC FEATURE COEXISTANCE was:([techfastint] usefulness of PUSHINT/POPINT from [techcodesize])
Thanks Tim, I think that sums it up nicely. I just wanted to put a pointer out to the original post that I made on isadev regarding opcode sharing / management: https://groups.google.com/a/groups.ris
Thanks Tim, I think that sums it up nicely. I just wanted to put a pointer out to the original post that I made on isadev regarding opcode sharing / management: https://groups.google.com/a/groups.ris

By
Guy Lemieux
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reminder, Vector task group meeting Friday
We'll meet per the calendar entry. Agenda is to go over any remaining unsettled open issues, Krste
We'll meet per the calendar entry. Agenda is to go over any remaining unsettled open issues, Krste

By
Krste Asanovic
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Vector Byte Arrangement in Wide Implementations 10 messages
I've been thinking through the cases where a wide implementation that wants "slices" could have to introduce a hiccup to rearrange bytes because of an EEW change (since SLEN is gone). The ones I know
I've been thinking through the cases where a wide implementation that wants "slices" could have to introduce a hiccup to rearrange bytes because of an EEW change (since SLEN is gone). The ones I know

By
Bill Huffman
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vector strided stores when rs1=x0 8 messages
Also on github as issue #595 In our earlier TG discussion in 9/18 meeting, we were in favor of allowing vector strided load instructions with rs1=x0 to perform fewer memory accesses than the number of
Also on github as issue #595 In our earlier TG discussion in 9/18 meeting, we were in favor of allowing vector strided load instructions with rs1=x0 to perform fewer memory accesses than the number of

By
Krste Asanovic
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Vector TG minutes from 2020/11/6 meeting
Also, reminder we'll be meeting tomorrow (Friday Nov 13) as per calendar entry (7 hours from now), Krste Date: 2020/11/06 Task Group: Vector Extension Chair: Krste Asanovic CoChair: Roger Espasa Numb
Also, reminder we'll be meeting tomorrow (Friday Nov 13) as per calendar entry (7 hours from now), Krste Date: 2020/11/06 Task Group: Vector Extension Chair: Krste Asanovic CoChair: Roger Espasa Numb

By
Krste Asanovic
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HalfPrecision, BFloat16, and Other Float Encoding: Reference Model Recommendations from Task Group 2 messages
In support of Open Source Software and publicly released modeling schemes, does the Vector Task Group have a recommendation for arithmetic reference? The published ISSs can provide checking results fr
In support of Open Source Software and publicly released modeling schemes, does the Vector Task Group have a recommendation for arithmetic reference? The published ISSs can provide checking results fr

By
CDS
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Vector TG minutes 2020/11/13 meeting
Date: 2020/11/13 Task Group: Vector Extension Chair: Krste Asanovic CoChair: Roger Espasa Number of Attendees: ~22 Current issues on github: https://github.com/riscv/riscvvspec Issues discussed: #
Date: 2020/11/13 Task Group: Vector Extension Chair: Krste Asanovic CoChair: Roger Espasa Number of Attendees: ~22 Current issues on github: https://github.com/riscv/riscvvspec Issues discussed: #

By
Krste Asanovic
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rename vfrece7/vfrsqrte7 to vfrec7 and vfrsqrt7 2 messages
This is issue #601. It was pointed out that *e7 (estimate to 7 bits) suffix on mnemonic is easily confused with e32 (element size 32) on other mnemonics. This is probably one we can handle on email th
This is issue #601. It was pointed out that *e7 (estimate to 7 bits) suffix on mnemonic is easily confused with e32 (element size 32) on other mnemonics. This is probably one we can handle on email th

By
Krste Asanovic
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next vector meeting in 7 hours
I think we'll be spending a chunk of time on mask layout and implementation issues. See you then, Krste
I think we'll be spending a chunk of time on mask layout and implementation issues. See you then, Krste

By
Krste Asanovic
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What is the plan for rvv v1.0 2 messages
Hi Krste and Andrew, What is the rough plan for rvv v1.0 release? I searched vectorext mailing list but can’t find the info I want. Thanks Weiwei
Hi Krste and Andrew, What is the rough plan for rvv v1.0 release? I searched vectorext mailing list but can’t find the info I want. Thanks Weiwei

By
Wang Weiwei
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回复: [RISCV] [techvectorext] What is the plan for rvv v1.0
That is exactly what I want. Thanks Mark. Weiwei 发件人: techvectorext@... <techvectorext@...> 代表 mark 发送时间: 2020年11月25日 23:13 收件人: Wang Weiwei <Weiwei.Wang@...> 抄送: vector <techvectorext@...> 主题:
That is exactly what I want. Thanks Mark. Weiwei 发件人: techvectorext@... <techvectorext@...> 代表 mark 发送时间: 2020年11月25日 23:13 收件人: Wang Weiwei <Weiwei.Wang@...> 抄送: vector <techvectorext@...> 主题:

By
Wang Weiwei
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Vector Task Group minutes 2020/11/20 meeting
Next meeting today in usual time slot as on calendar, Krste Date: 2020/11/20 Task Group: Vector Extension Chair: Krste Asanovic CoChair: Roger Espasa Number of Attendees: ~17 Current issues on github
Next meeting today in usual time slot as on calendar, Krste Date: 2020/11/20 Task Group: Vector Extension Chair: Krste Asanovic CoChair: Roger Espasa Number of Attendees: ~17 Current issues on github

By
Krste Asanovic
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The scenarios of GEMM for u/int8 data 3 messages
Hi，all Recently, I optimized the kernel of GEMM for int8 data. I found that there was no good solution to do in by the use of the present vector ISA. The mainly difficult I meet is: The accumulator is
Hi，all Recently, I optimized the kernel of GEMM for int8 data. I found that there was no good solution to do in by the use of the present vector ISA. The mainly difficult I meet is: The accumulator is

By
Linjie Yu
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答复: [RISCV] [techvectorext] The scenarios of GEMM for u/int8 data
Hi，David Can we see the git of your work? My code has not been upload to git, and I will show it in the mail. Does this mean the 32 vector registers are not enough, or that the number of elements for
Hi，David Can we see the git of your work? My code has not been upload to git, and I will show it in the mail. Does this mean the 32 vector registers are not enough, or that the number of elements for

By
Linjie Yu
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Vector Task Group minutes 2020/12/04 17 messages
Date: 2020/12/04 Task Group: Vector Extension Chair: Krste Asanovic CoChair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscvvspec Note: No meeting wee
Date: 2020/12/04 Task Group: Vector Extension Chair: Krste Asanovic CoChair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscvvspec Note: No meeting wee

By
Krste Asanovic
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Last vector TG meeting of 2020, usual time, Friday Dec 17
Agenda is hopefully clearing up any remaining major issues before 1.0 draft can go out, Krste
Agenda is hopefully clearing up any remaining major issues before 1.0 draft can go out, Krste

By
Krste Asanovic
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Vector Extension Workgroup Meeting 2 messages
I don’t see Vector Extension meetings on the calendar. Is the group meeting? Bill Bill Huffman Distinguished Engineer T: 408.944.7613
I don’t see Vector Extension meetings on the calendar. Is the group meeting? Bill Bill Huffman Distinguished Engineer T: 408.944.7613

By
Bill Huffman
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About vmv.x.s should be vs1 = 0?
I see it on riscvvspec commit: 0e8cdeb26bb98de2b1089d79a681af2c5a65e712 vmv.x.s rd, vs2 # x[rd] = vs2[0] (rs1=0) vmv.x.s belong to VWXUNARY0 and OPMVV But OPMVV has only vs1 no rs1, see : funct6  v
I see it on riscvvspec commit: 0e8cdeb26bb98de2b1089d79a681af2c5a65e712 vmv.x.s rd, vs2 # x[rd] = vs2[0] (rs1=0) vmv.x.s belong to VWXUNARY0 and OPMVV But OPMVV has only vs1 no rs1, see : funct6  v

By
yahan@...
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