Date   
Vector TG Meeting Minutes 2021/07/09 By Krste Asanovic ·
Zve should be a strict subset of V, use new option to relax VLEN 5 messages By Guy Lemieux ·
Multiple accesses required to the same location for strided memory accesses By Bill Huffman ·
回复:[RISC-V] [tech-vector-ext] Configuring qemu for Vector Extension By LIU Zhiwei ·
Clarification of Fractional LMUL requirements, and the storage/derivation of ELEN/SEWLMUL1MAX values 2 messages By Gregory Kielian ·
Specify byte index/offset for Strided/Indexed instructions. Minor document improvement RISC-V "V" Vector Extension Version 1.0-rc1-20210608 By Tony Cole ·
vwredsum 3 messages By Earl Killian ·
Vector spec v1.0-rc2 By Krste Asanovic ·
Vector 1.0 ready for public review By Krste Asanovic ·
Configuring qemu for Vector Extension 12 messages By Mick Thomas Lim ·
Is it safe to extend LMUL's maximum value based on current rc2 version? 3 messages By Feng Chuang ·
Basic options for chaining vector loads? 2 messages By Arjan Bink ·
reliably set vtype.vill 9 messages By Tim Newsome ·
RISC-V Vector Extension post-public review updates - 32bit opcode decision By David Horner ·
RISC-V Vector Extension post-public review updates 39 messages By Krste Asanovic ·
RISC-V Vector Extension post-public review updates - fault flagging 14 messages By David Horner ·
RVV assembler and simulation 2 messages By Peter Lieber ·
Vector Memory Ordering 16 messages By Bill Huffman ·
FP Trapped exceptions needed for portability 2 messages By Ken Dockser ·
[EXT] Re: [RISC-V] [tech-vector-ext] FP Trapped exceptions needed for portability By Jeff Scott ·