I've been wading through the fractional LMUL discussion on github but believe the simple basic solution below meets the immediate needs, without blocking possible reuse of unused register fields later

I am developing sparse matrix codes using the vector extension on RISCV32 using SPIKE simulator. Based on my understanding of the spec thus far, I wanted to ask a couple of questions about the spec. I

We will be meeting again this morning. I hope to focus on closing on features for upcoming 0.9 release. Krste

Hi，all I have some applications about byte/halfword/word vector load/stores, like gemm, direct convolution and son on. For 3x3 direct convolution, the code without byte/halfword/word vector load/store

The number of instructions does not necessarily correspond to the speed, and especially not to the PPA or efficiency. Making the load/store simpler might save enough area to make it as or more energy

Hi Damon, Thanks for providing a concrete example! I think you can improve the performance of your first example (non-widening loads). Instead of immediately widening, you could instead perform your s

I agree with your point. But nowadays, the spec is not stable, and there is no target SOC to verify it. So, in my opinion, the number of instructions is an important indicator at present. 发件人: Bruce H

Hi, Nick That is a good suggestion for my code, thank you very much. But I develop my code depend on spec 0.7.1. The q-wide instructions had not been added to the spec. And I am confused with the upda

Hi, all I have a problem about the usage of VectorAMO Operations. In the spec, there is only two sentences to describe the usageof Vector AMO Operations. Who have the concrete sample or other applicat

Date: 2020/4/03 Task Group: Vector Extension Chair: Krste Asanovic Number of Attendees: ~15 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed: #354/362 The following iss

Previous issues I opened on fractional LMUL were exploratory, suggesting various ways to encode and enable the feature. The latest 4 issues opened on github are specific proposals based on the strawma

Also a reminder that the next meeting will be a half hour earlier. Please check the group's calender for details. Krste Date: 2020/4/17 Task Group: Vector Extension Chair: Krste Asanovic Number of Att

There are two separate issues noted with the proposal to fixed-size vector load/stores. One is the additional vsetvli instructions needed, and the second is the additional widening instructions requir

I added my proposal to github: https://github.com/riscv/riscv-v-spec/issues/425 appended below for those not following github Krste This proposal is a modification of earlier idea to add effective ele

Thank you very much for this. I started a pull request, but was including as an extension and still debating the best way to incorporate. Would it be possible to generate a pdf for what is now a subst

First some observations from the revised LMUL. *1 The format for a given SLEN and SEW is the same for all LMUL>=1 *2 LMUL=n is equivalent to LMUL=2 * n with vl < 1/2 vlmax at that level, for n=1,2,4.

The aspect that will probably be most problematic for programmer is the loss of memory mapping paradigm. Whereas adjacent bytes in memory are in the same or adjacent words (ditto for half words and do

I've been busy trying to get to a draft of 0.9. I just pushed a set of memory instructions with "effective element width" encoded statically, though the text needs more read through and checking. We'l

Date: 2020/5/1 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~20 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed: #440

We’ll be meeting tomorrow morning. Meeting details on member calendar. Krste (on iPhone, forgive terseness)