I've made a major update to mask encoding, pushed to repo. The earlier change to support fractional LMUL effectively "broke" the earlier mask encoding. The new scheme is simpler, but is different. Ple

I believe this can be weakened to required: select-able distribution patterns that are sufficiently compatible that they avoid fragmenting the software ecosystem.

I have some suggestions for the reasons for moving from v0.8 vertical striping to v0.9 horizontal SLEN (interleave) Under v0.8 A) when vl < VLEN/SEW*LMUL the top elements are not filled. This can lead

I made this into its own thread as well. I think there is a parallel in the in-register/in-memory issue and memory consistency model/methods. The complexity of consistency models and methods is enormo

Reminder we have our TG meeting this Friday morning. Details on member calendar. Krste

Hi, We, EPI, SiPearl, and SiFive, have come out with a RFC for vector intrinsics. Although there are still some issues under discussion, we think it is time to publish the document to collect more fee

Date: 2020/5/15 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~20 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed: # M

There hasn't been any traffic on this feed about vector layout, and specifically about v0.9 SLEN size standards. So I will add my thoughts here with the hopes that I will not take excessive time durin

I finally pushed minutes of last meeting (attached) Our next meeting is later today (Friday Jun 12) with details available on task group calendar. I’m preparing a note on vector register layout, which

Hi all, In this page I would like to discuss about fault-only-first indexed load instructions since we have certain using cases, for example, SPEC CPU 2006 4.1.bzip2 src/blocksort.c:line 712. For faul

We agreed to meet again today (Friday) in usual slot - see member calendar for details, Krste Date: 2020/6/12 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attend

Attached below. Also a reminder we'll be meeting again on Friday per group's calendar info. Krste Date: 2020/6/19 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of At

The whole register loads and stores in section 7.9 of the spec are currently specified as having an element size of 8-bits. Could they be extended to cover all sizes instead of just the 8-bit size? It

TL;DR: I'm leaning towards mandating SLEN=VLEN layout, at least for application processor profiles. Regarding register layout, I thought it would be good to lay out the landscape and comparison with o

We’ll be meeting later today per the member calendar, Krste

In case you missed it, yesterday the HPC community announced the "world's fastest computer" (based on Linpack) is based on the Fujitsu A64FX, which is the first to implement the ARM Scalable Vector Ex

Date: 2020/6/26 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~15 Current issues on github: https://github.com/riscv/riscv-v-spec Thanks to all the par

I made a pass over the spec repo, adding red labels for “resolve for v1.0’ , versus yellow labels for "resolve after v1.0”. I also cleaned up and closed some other issues. "Resolve after’ should not b

I don't agree that #478 should be closed for the reasons given. I do agree that another approach might be better to superseded that which was originally proposed. But I do not agree with the proposed

I disagree that #460 should be deferred until after V1.0. Although I agree that the proposal itself can be implemented in a manner consistent with the current vsetvli definition, I disagree that the l