minor typos; substantial correction: also throughout the email vd should be rd vs1 should be rs1 And vs2 is completely bogus. Sorry I didn't catch this sooner.

Sorry for what may be a question with an answer that may be obvious to those that have been at all the meetings: Have the vector-scalar instructions (.vs) been eliminated from the vector extensions? B

TL;DR; I make clarifications on meeting minutes. I propose we present 1) a relaxed RVV memory/process model, more relaxed than we believe current implementations require for optimal performance. Appli

I trust this is not just noise. A laundry list of concerns Assess objectives and those met as we approach v1.0 of RVV Polymorphism has not made it into RVV V0.9 Tagging registers with a datatype is no

I added a note on this issue to spec: NOTE: When migrating a software thread between two harts with different microarchitectures, the `vstart` value might not be supported by the new hart microarchite

I realize it is a holiday in US today, but I will hold a vector TG meeting for those who can attend in usual slot as given in member calendar. I've been updating the spec with earlier decisions, and t

Date: 2020/7/03 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~6 Current issues on github: https://github.com/riscv/riscv-v-spec This call was sparsely

There are 19 open issues that aren't yet labeled. Does it make sense that those who will be on the call review them with an idea to categorize as for or after V1.0? That should also determine those th

I messed up the links: the list of open unlabeled issues is here: https://github.com/riscv/riscv-v-spec/issues?q=is%3Aissue+is%3Aopen+no%3Alabel

We’ll have our regular TG meeting in a few hours per member calendar. We’ll continue to clean up remaining issues for v1.0, Krste

A belated posting of minutes from last week's meeting. We'll be meeting again today as per member calendar, Krste Date: 2020/7/03 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Esp

I managed to swap the file names around, and sent earlier week's minutes instead of last week's. Here's the correct minutes from last week (also fixed in repo). Krste Date: 2020/7/10 Task Group: Vecto

Date: 2020/7/17 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~20 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed: #39

This was on Github; as not every one subscribes and it will be considered at TG, I include it on this list. First Krste’s synopsys, then my (modified) Github reply, then my thoughts for the TG and las

Hi all, For some certain cases such as histogram we might have duplicate runtime memory dependences, and the current V extension may fail to vectorize such cases. Therefore, I would like to propose du

I want to bring this to group's attention as I think I've convinced myself that Guy's suggestion is the correct path to follow, i.e., vsetvli x0, x0, imm will raise vill if the new SEW'/LMUL' ratio is

Date: 2020/7/24 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~18 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed: # B

RISC V needs CMOs, and hence a CMO Working Group EditNew Page All successful computer instruction sets have Cache Management Operations (CMOs). Several RISC-V systems have already defined implementati

I posted a comment to the closed #427 Not everyone subscribes to GitHub, so I post it below, I am requesting this proposal be reconsidered/re-evaluated for V1.0 inclusion in light of the posting: Some

Is the point of vrsub.vi to provide negation? From a compiler/user perspective, completing the vsub pattern with vsub.vi (even as a virtual instruction) may be a usability enhancement to consider.