The meeting minutes in added in the note. You can also find it under riscv-admin/rvv-intrinsics.

Hi all, A reminder that the next open meeting to discuss on the RISC-V V C Intrinsic API v1.0 release is going to be held on 2022/11/28 6AM (GMT -7) / 11PM (GMT +8). For folks in Asia, be noted that t

A few issues have been identified in corners of the vector spec. The first change was an error of omission in not catching some cases of source and destination register overlap that can not be sensibl

The second fix is just a clarification of a missing case in the spec: "vsetvl[i] with rd=rs1=x0 is reserved if vill was 1 beforehand." The "vsetvl[i] x0, x0" form is defined in terms of whether VLMAX

Hi all, A reminder that the next open meeting to discuss on the RISC-V V C Intrinsic API v1.0 release is going to be held on 2022/10/31 7AM (GMT -7) / 10PM (GMT +8). The agenda can be found in the sec

From: Krste Asanovic via lists.riscv.org Sent: Thursday, October 6, 2022 12:42 PM We can delay, but not prevent, the need to have greater than 32b instructions. I worked on another RISC ISA for 25+ ye

These RISC-V vector extensions to handle IEEE FP16 were defined prior to ratification of the vector specification, but were left out of RVV 1.0 as they were not to be included in the base V extension.

Hi all, A reminder that an open meeting to draft the RISC-V V C Intrinsic API v1.0 release is going to be held later on 2022/10/03 7AM (GMT -7) / 10PM (GMT +8). Slide has been posted and agenda is in

+sig-vector@...

I've been working up a scheme to handle vector element groups in general, with vector crypto being the first anticipated use case. This replaces the EDIV concept with a more general group concept that

Hi all, A reminder that an open meeting to draft the RISC-V V C Intrinsic API v1.0 release is going to be held on next Monday 2022/09/05 7AM (GMT -7) / 10PM (GMT +8). The planned agenda will be to hav

Hi all, As mentioned in the first RFC letter, here we want to share our draft roadmap for the formal release. The main goal of this release is to stablize the using environment of the RVV C intrinsics

Hi all, We (SiFive) are going to draft out a formal v1.0 release for the RVV C intrinsic API. Next week we are going to provide a roadmap, including time reserved for comments on what is left on the t

Community members, The Vector Extension Task Group community has completed its work and is slated to be deactivated and archived on August 15, 2022. If you believe that this decision has been made in

Hi: I am Kito from the RISC-V psABI group, we've defined a basic vector ABI, which allows function use vector registers within function, that could be used for optimize several libraries like libc, e.

Hello all, I hope you are fine, safe, and healthy. I want to know if there is any test suite or platform which can be used to run RISC-V Vector compliance tests? We, in our team, have started to work

1. Question for tail bits of mask-producing instructions. In the case of mask-producing instructions, tail elements are the bits with (vl <= bit index < VLEN).So according to riscv-v-spec-1.0, page 46

I am hearing renewed interest in adding a dot-product extension to the RISC-V Vectors. This includes everything from adding a handful of FP and Int dot-product instructions all the way to completing t

Hello! I have a question about vector segment load and stores. In table 14 we have NFIELDS from 1 to 8. In paragraphes 7.8.1-3 we have format like vlseg<nf>e<eew>.v vd, (rs1), vm vsseg<nf>e<eew>.v vs3

Hi， I have a question about masked-off bits. I am not sure what is the behavior of destination inactive masked-off bits for instructions vmsbf.m, vmsif.m, vmsof.m. Does the "xxxx" means we can fill an