I've been thinking through the cases where a wide implementation that wants "slices" could have to introduce a hiccup to rearrange bytes because of an EEW change (since SLEN is gone). The ones I know

We'll meet per the calendar entry. Agenda is to go over any remaining unsettled open issues, Krste

Thanks Tim, I think that sums it up nicely. I just wanted to put a pointer out to the original post that I made on isa-dev regarding opcode sharing / management: https://groups.google.com/a/groups.ris

I am now investigating how to efficiently implement sparse matrix X (dense) vector multiplications (spMV) using RISCV vectors using bit-vector format of compressing the sparse matrix. The inner loop o

These are all important considerations. However, what they have in common when considering Allen's question: is that they are all tactical considerations are in the context of our current framework of

I'm working through updates to vector spec, and one part of clean up is changing text where it has mandatory raising of illegal instruction exceptions on unsupported encodings to instead state the enc

Reminder: No meeting next Friday October 30. Date: 2020/10/23 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://githu

Forwarding this to tech-vector-ext; couple comments below. Indeed, I've found other microarchitectural reasons to favor this approach (e.g., speculating through mask-register values). Enumerating all

Date: 2020/10/16 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~16 Current issues on github: https://github.com/riscv/riscv-v-spec # Definition of Done

Hi, what is a reasonable sequence to insert an element into an arbitrary position in the vector? I considered the following sequence (assume the input vector is v12) vid.v v1 vmseq.vx v0, v1, <index>

Date: 2020/10/9 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscv-v-spec # 576 vlsegff excepti

Date: 2020/10/2 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed; # I

Per calendar instructions, in usual time slot, Proposed agenda: #560 vmulh rounding mode #576 vlsegff exception behavior #550 names/contents of initial vector subsets #568 disabling/context swtiching

Vector Extension Task Group Meeting When: Friday, 12 June 2020 8:00am to 9:00am (UTC-07:00) America/Los Angeles Repeats: Weekly on Friday, through Thursday, 8 October 2020 Organizer: Krste Asanovic kr

Should vid.v raise an illegal instruction exception when masked and when the destination group overlaps v0 ? Should vid.v raise an illegal instruction exception when vstart > 0 ?

Krste

Reminder we’ll be meeting tomorrow in usual slot. I’d like to spend the time discussing imprecise trap handling for embedded vector systems. Hopefully, we can all see the new correct link on Google Ca

In the latest vector proposal (draft of version 1.0), there is the following restriction on widening instructions (section 11.2) For all widening instructions, the destination EEW and EMUL values must

Date: 2020/9/25 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~14 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed #551

Krste