Hi Krste and Andrew, What is the rough plan for rvv v1.0 release? I searched vector-ext mailing list but can’t find the info I want. Thanks Weiwei

I think we'll be spending a chunk of time on mask layout and implementation issues. See you then, Krste

This is issue #601. It was pointed out that *e7 (estimate to 7 bits) suffix on mnemonic is easily confused with e32 (element size 32) on other mnemonics. This is probably one we can handle on email th

Date: 2020/11/13 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~22 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed: #

In support of Open Source Software and publicly released modeling schemes, does the Vector Task Group have a recommendation for arithmetic reference? The published ISSs can provide checking results fr

Also, reminder we'll be meeting tomorrow (Friday Nov 13) as per calendar entry (7 hours from now), Krste Date: 2020/11/06 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Numb

Also on github as issue #595 In our earlier TG discussion in 9/18 meeting, we were in favor of allowing vector strided load instructions with rs1=x0 to perform fewer memory accesses than the number of

I've been thinking through the cases where a wide implementation that wants "slices" could have to introduce a hiccup to rearrange bytes because of an EEW change (since SLEN is gone). The ones I know

We'll meet per the calendar entry. Agenda is to go over any remaining unsettled open issues, Krste

Thanks Tim, I think that sums it up nicely. I just wanted to put a pointer out to the original post that I made on isa-dev regarding opcode sharing / management: https://groups.google.com/a/groups.ris

I am now investigating how to efficiently implement sparse matrix X (dense) vector multiplications (spMV) using RISCV vectors using bit-vector format of compressing the sparse matrix. The inner loop o

These are all important considerations. However, what they have in common when considering Allen's question: is that they are all tactical considerations are in the context of our current framework of

I'm working through updates to vector spec, and one part of clean up is changing text where it has mandatory raising of illegal instruction exceptions on unsupported encodings to instead state the enc

Reminder: No meeting next Friday October 30. Date: 2020/10/23 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://githu

Forwarding this to tech-vector-ext; couple comments below. Indeed, I've found other microarchitectural reasons to favor this approach (e.g., speculating through mask-register values). Enumerating all

Date: 2020/10/16 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~16 Current issues on github: https://github.com/riscv/riscv-v-spec # Definition of Done

Hi, what is a reasonable sequence to insert an element into an arbitrary position in the vector? I considered the following sequence (assume the input vector is v12) vid.v v1 vmseq.vx v0, v1, <index>

Date: 2020/10/9 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscv-v-spec # 576 vlsegff excepti

Date: 2020/10/2 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed; # I

Per calendar instructions, in usual time slot, Proposed agenda: #560 vmulh rounding mode #576 vlsegff exception behavior #550 names/contents of initial vector subsets #568 disabling/context swtiching