From 0.9 stable spec, 5.3.1, table (no number), vector masking is referred to as having LSB. This suggests, yet does not require, that the mask field for each element is greater than bit-size 1. From

Hi team, Do we have a plan to write a V-extension white paper? Is there any interest? I'm thinking along the lines of ARM's SVE paper in IEEE Micro '17. I don't know if this is feasible or appropriate

Date: 2020/9/18 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~17 Current issues on github: https://github.com/riscv/riscv-v-spec #551 Memory orderings

Date: 2020/9/4 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~20 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed: Spec

Date: 2020/8/21 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed: #50

Ahead of the vector meeting I would like to see if we can address or at least get direction on some of the flagged for pre-v1.0 resolution. There are 3 related flagged issues that all deal with vstart

I believe I added the correct zoom info on the correct new calendar for tomorrow’s vector task group meeting. Please check and advise if you’re not seeing it, Krste

i was made aware of this paper. risc-v vectors are mentioned. one of the key conclusions are (from the abstract) Our experiments show that VLA code reaches about 90% of the performance of vector lengt

Reminder there’s no vector TG meeting tomorrow (I have a conflict). We’ll be meeting again on Friday Sep 18 (I’ll work with Stephano to figure out new calendar scheme), Krste

what are the use cases? do we have examples in mind when they would/could be used? are there examples of what developers would want from previous efforts on vector machines? can we write them down? th

Though I don’t know if we’re affected by calendar changes, Krste

From chapter 11, section 1 (#3): The 5-bit immediate is unsigned when either providing a register index in vrgather or a count for shift, clip, or slide. In all other cases it is signed and sign exten

Hi all, For common AI workloads such as DNNs, data communications between network layers introduce huge pressure on capacity and bandwidth of the memory hierarchy. For instance, dynamic large activati

Hi all, I understand the EEW, as explicitly encoded in the load/store instructions applies to the vector of indices for the indexed loads and stores. For instance we can load a vector "SEW=8,LMUL=1" u

Sorry for late notice, but I have to cancel the vector tech meeting today, Krste

I am pleased to announce that our/SiFive's RVV intrinsic enabled GCC are open-sourced now. We put the sources on riscv's github, and the RVV intrinsics have been integrated in the riscv-gnu-toolchain,

Apologies if this is old stuff already dismissed. But I give it a try anyway. Wouldn't it make sense to separate more complex vector instructions from more trivial ones? Already with the very first ba

(I've been having email problems.)

The task group has recommended moving forward with adding instructions that estimate reciprocals and reciprocal square roots. These are both useful for -ffast-math code where it's acceptable to sacrif

Cancelled: Vector Extension Task Group Meeting This event has been cancelled. When: Friday, 14 August 2020 8:00am to 9:00am (UTC-07:00) America/Los Angeles Organizer: Krste Asanovic krste@... Descript