Apologies for late notice, but I’m going to cancel the vector TG meeting today. I still have a backlog of settled issues to incorporate in document, and do not have a set of topics worked up for this

Vector-widening multiply & accumulate instructions: These instructions, signed or unsigned, will quickly overflow in even simple cases. Given absence of flagging (e.g. OVERFLOW), a saturating version

The definition of the numeric range (at the beginning of section 13) matches the definition of an integer, not of a fixed-point number. For example, the range specified is the range of an integer, not

Date: 2020/8/7 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~22 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed: #549

Apologies for delay in sending these out. When doing this week's minutes, I realized I hadn't sent out previous week's. Krste Date: 2020/7/31 Task Group: Vector Extension Chair: Krste Asanovic Co-Chai

Is the point of vrsub.vi to provide negation? From a compiler/user perspective, completing the vsub pattern with vsub.vi (even as a virtual instruction) may be a usability enhancement to consider.

I posted a comment to the closed #427 Not everyone subscribes to GitHub, so I post it below, I am requesting this proposal be reconsidered/re-evaluated for V1.0 inclusion in light of the posting: Some

RISC V needs CMOs, and hence a CMO Working Group EditNew Page All successful computer instruction sets have Cache Management Operations (CMOs). Several RISC-V systems have already defined implementati

Date: 2020/7/24 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~18 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed: # B

I want to bring this to group's attention as I think I've convinced myself that Guy's suggestion is the correct path to follow, i.e., vsetvli x0, x0, imm will raise vill if the new SEW'/LMUL' ratio is

Hi all, For some certain cases such as histogram we might have duplicate runtime memory dependences, and the current V extension may fail to vectorize such cases. Therefore, I would like to propose du

This was on Github; as not every one subscribes and it will be considered at TG, I include it on this list. First Krste’s synopsys, then my (modified) Github reply, then my thoughts for the TG and las

Date: 2020/7/17 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~20 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed: #39

I managed to swap the file names around, and sent earlier week's minutes instead of last week's. Here's the correct minutes from last week (also fixed in repo). Krste Date: 2020/7/10 Task Group: Vecto

A belated posting of minutes from last week's meeting. We'll be meeting again today as per member calendar, Krste Date: 2020/7/03 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Esp

We’ll have our regular TG meeting in a few hours per member calendar. We’ll continue to clean up remaining issues for v1.0, Krste

I messed up the links: the list of open unlabeled issues is here: https://github.com/riscv/riscv-v-spec/issues?q=is%3Aissue+is%3Aopen+no%3Alabel

There are 19 open issues that aren't yet labeled. Does it make sense that those who will be on the call review them with an idea to categorize as for or after V1.0? That should also determine those th

Date: 2020/7/03 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~6 Current issues on github: https://github.com/riscv/riscv-v-spec This call was sparsely

I realize it is a holiday in US today, but I will hold a vector TG meeting for those who can attend in usual slot as given in member calendar. I've been updating the spec with earlier decisions, and t