From chapter 11, section 1 (#3): The 5-bit immediate is unsigned when either providing a register index in vrgather or a count for shift, clip, or slide. In all other cases it is signed and sign exten

Hi all, For common AI workloads such as DNNs, data communications between network layers introduce huge pressure on capacity and bandwidth of the memory hierarchy. For instance, dynamic large activati

Hi all, I understand the EEW, as explicitly encoded in the load/store instructions applies to the vector of indices for the indexed loads and stores. For instance we can load a vector "SEW=8,LMUL=1" u

Sorry for late notice, but I have to cancel the vector tech meeting today, Krste

I am pleased to announce that our/SiFive's RVV intrinsic enabled GCC are open-sourced now. We put the sources on riscv's github, and the RVV intrinsics have been integrated in the riscv-gnu-toolchain,

Apologies if this is old stuff already dismissed. But I give it a try anyway. Wouldn't it make sense to separate more complex vector instructions from more trivial ones? Already with the very first ba

(I've been having email problems.)

The task group has recommended moving forward with adding instructions that estimate reciprocals and reciprocal square roots. These are both useful for -ffast-math code where it's acceptable to sacrif

Cancelled: Vector Extension Task Group Meeting This event has been cancelled. When: Friday, 14 August 2020 8:00am to 9:00am (UTC-07:00) America/Los Angeles Organizer: Krste Asanovic krste@... Descript

Apologies for late notice, but I’m going to cancel the vector TG meeting today. I still have a backlog of settled issues to incorporate in document, and do not have a set of topics worked up for this

Vector-widening multiply & accumulate instructions: These instructions, signed or unsigned, will quickly overflow in even simple cases. Given absence of flagging (e.g. OVERFLOW), a saturating version

The definition of the numeric range (at the beginning of section 13) matches the definition of an integer, not of a fixed-point number. For example, the range specified is the range of an integer, not

Date: 2020/8/7 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~22 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed: #549

Apologies for delay in sending these out. When doing this week's minutes, I realized I hadn't sent out previous week's. Krste Date: 2020/7/31 Task Group: Vector Extension Chair: Krste Asanovic Co-Chai

Is the point of vrsub.vi to provide negation? From a compiler/user perspective, completing the vsub pattern with vsub.vi (even as a virtual instruction) may be a usability enhancement to consider.

I posted a comment to the closed #427 Not everyone subscribes to GitHub, so I post it below, I am requesting this proposal be reconsidered/re-evaluated for V1.0 inclusion in light of the posting: Some

RISC V needs CMOs, and hence a CMO Working Group EditNew Page All successful computer instruction sets have Cache Management Operations (CMOs). Several RISC-V systems have already defined implementati

Date: 2020/7/24 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~18 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed: # B

I want to bring this to group's attention as I think I've convinced myself that Guy's suggestion is the correct path to follow, i.e., vsetvli x0, x0, imm will raise vill if the new SEW'/LMUL' ratio is

Hi all, For some certain cases such as histogram we might have duplicate runtime memory dependences, and the current V extension may fail to vectorize such cases. Therefore, I would like to propose du