Hello all, I hope you are fine, safe, and healthy. I want to know if there is any test suite or platform which can be used to run RISC-V Vector compliance tests? We, in our team, have started to work

1. Question for tail bits of mask-producing instructions. In the case of mask-producing instructions, tail elements are the bits with (vl <= bit index < VLEN).So according to riscv-v-spec-1.0, page 46

I am hearing renewed interest in adding a dot-product extension to the RISC-V Vectors. This includes everything from adding a handful of FP and Int dot-product instructions all the way to completing t

Hello! I have a question about vector segment load and stores. In table 14 we have NFIELDS from 1 to 8. In paragraphes 7.8.1-3 we have format like vlseg<nf>e<eew>.v vd, (rs1), vm vsseg<nf>e<eew>.v vs3

Hi， I have a question about masked-off bits. I am not sure what is the behavior of destination inactive masked-off bits for instructions vmsbf.m, vmsif.m, vmsof.m. Does the "xxxx" means we can fill an

Hi,all Debuggers can use abstract commands to access CSRs. When using abstract commands, debuggers need to specify the bit width of CSRs. The bit widths of vcsr and vstart are not clearly defined in V

Yes, this would be the obvious path to take. Some use cases, including maybe this one, might prefer FP traps to be horizontal into user mode. There is the old MIPS FPU pipeline trick of conservative e

Completely agree. Was very happy RISC-V did not include FPU exceptions. Jeff

While I understand that it had been decided long ago (relatively speaking) that RISC-V would not support trapping on floating-point exceptions, I am wondering if we need to revisit this. I have heard

I think from this morning, we are considering: Ordered scatters are done truly in order Strided stores that overlap (including segmented ones) will trap as illegal All other vector loads and stores do

I am working on some experiment and I need to simulate RVV r1.0. Is spike my best bet for this? All I want to start with is writing bare metal assembly, and copy some memory buffers between the sim an

However, we did discuss its merit; if it would trump the encoding dificulties, see below - there are two aspects here - a) checking array indexes are within bounds, which absent proof that the indexes

Apart from requests for more instructions, which can be handled with later extensions, there were no real substantive updates. I did notice one issue at end of public review, however. The current spec

Yes, absolutely. Many vector models historically have been co-processors with their own internal status. RVV integration is also a major accomplishment. I was a part of that. However, a consensus with

I'm trying to set vill, and I can't think of a reliable way to do it. This comes up when OpenOCD (a debugger) connects to a RV32 target where vtype contains (for instance) 0x80000000. The user asks to

Hello all, Could somebody please comment on the basic options related to chaining vector loads? It is easy to see how arithmetic vector instructions can be chained together. However, if a vector load

hi Krste and all friends, Per my understanding, if I extend the vector architecture register number (to be larger than 32) and extend maximum LMUL value to be larger than 8, current vector extension (

Does a known-good guide exist for building riscv64 qemu to be able to run Vector instructions? From the main qemu repo, we are to build the riscv64-softmmu target and run the 64-bit Buildroot Image, a

I’ve made a frozen release of version 1.0 ready for public review. The release is tagged: https://github.com/riscv/riscv-v-spec/releases/tag/v1.0 and I’ve attached pdf below. The main repo has now adv

I've finally finished an extensive pass over the whole spec, and believe it should be ready for public review but given that it's late on a Friday, I would like to give at least one more sleep cycle b