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[tech-vector-ext] Some proposals
2 messages
It doesn't look like all these issues were addressed either on mailing list or on github tracker. In general, it is much better to split feedback into individual topics. I'm responding all-in-one belo
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It doesn't look like all these issues were addressed either on mailing list or on github tracker. In general, it is much better to split feedback into individual topics. I'm responding all-in-one belo
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By
Krste Asanovic
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[tech-vector-ext] Feedback on RISC-V V-extension (FFTW3 and Chacha20)
We have seen very efficient FFT execution without adding new instructions, but there is interest in a layer of DSP extension on top of the base vector ISA. One goal of the EDIV extension would be to s
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We have seen very efficient FFT execution without adding new instructions, but there is interest in a layer of DSP extension on top of the base vector ISA. One goal of the EDIV extension would be to s
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By
Krste Asanovic
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Minutes of 2020/3/6 vector task group meeting
3 messages
Date: 2020/3/6 Task Group: Vector Extension Chair: Krste Asanovic Number of Attendees: ~21 Current issues on github: https://github.com/riscv/riscv-v-spec Note, the Zoom meeting details have changed.
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Date: 2020/3/6 Task Group: Vector Extension Chair: Krste Asanovic Number of Attendees: ~21 Current issues on github: https://github.com/riscv/riscv-v-spec Note, the Zoom meeting details have changed.
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By
Krste Asanovic
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Reminder vector TG meeting Friday March 6th, details on members calendar <eom>
By
Krste Asanovic
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Minutes from 2/21 meeting
Date: 2020/2/21 Task Group: Vector Extension Chair: Krste Asanovic Number of Attendees: ~13 Current issues on github: https://github.com/riscv/riscv-v-spec Note, the Zoom meeting details have changed.
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Date: 2020/2/21 Task Group: Vector Extension Chair: Krste Asanovic Number of Attendees: ~13 Current issues on github: https://github.com/riscv/riscv-v-spec Note, the Zoom meeting details have changed.
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By
Krste Asanovic
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EPI intrinsics reference and compiler updated to 0.8
Hi all, we have updated to version 0.8 of V-ext our LLVM-based experimental compiler and the intrinsics reference. EPI builtins and examples: https://repo.hca.bsc.es/gitlab/rferrer/epi-builtins-ref Co
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Hi all, we have updated to version 0.8 of V-ext our LLVM-based experimental compiler and the intrinsics reference. EPI builtins and examples: https://repo.hca.bsc.es/gitlab/rferrer/epi-builtins-ref Co
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By
Roger Ferrer Ibanez
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RISC-V Vector Task Group: fractional LMUL
5 messages
In the last meeting, we discussed a problem that would be introduced if we were to drop the fixed-size (b/h/w) variants of the vector load/stores and only have the SEW-size (e) variants. From the minu
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In the last meeting, we discussed a problem that would be introduced if we were to drop the fixed-size (b/h/w) variants of the vector load/stores and only have the SEW-size (e) variants. From the minu
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By
Krste Asanovic
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updates to vector spec repo on github
I added the change to add a vcsr including FP fields (this came out much cleaner I think) - please check over. Another minor change was to fold in the suggestion to move VS to a two-bit wide gap lower
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I added the change to add a vcsr including FP fields (this came out much cleaner I think) - please check over. Another minor change was to fold in the suggestion to move VS to a two-bit wide gap lower
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By
Krste Asanovic
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Minutes from 2020/1/24 meeting
Date: 2020/1/24 Task Group: Vector Extension Chair: Krste Asanovic Number of Attendees: ~20 github: https://github.com/riscv/riscv-v-spec Outstanding items from prior meeting: #362/#354, #341, #348, #
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Date: 2020/1/24 Task Group: Vector Extension Chair: Krste Asanovic Number of Attendees: ~20 github: https://github.com/riscv/riscv-v-spec Outstanding items from prior meeting: #362/#354, #341, #348, #
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By
Krste Asanovic
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Slidedown overlapping of dest and source regsiters
7 messages
The slideup instruction has this restriction: The destination vector register group for vslideup cannot overlap the source vector register group or the mask register, otherwise an illegal instruction
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The slideup instruction has this restriction: The destination vector register group for vslideup cannot overlap the source vector register group or the mask register, otherwise an illegal instruction
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By
Thang Tran
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Calling Convention for Vector ?
8 messages
Hi, Anyone know extra designed ABI information (like Calling Convention) about for vector register ? --Jojo
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Hi, Anyone know extra designed ABI information (like Calling Convention) about for vector register ? --Jojo
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By
"戎杰杰
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official v0.8 release of vector spec reference simulator
Krste, Roger We have just released an update of our free riscvOVPsim reference simulator version: 20191217.0 and put it on the https://github.com/riscv/riscv-ovpsim. riscvOVPsim supports the full late
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Krste, Roger We have just released an update of our free riscvOVPsim reference simulator version: 20191217.0 and put it on the https://github.com/riscv/riscv-ovpsim. riscvOVPsim supports the full late
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By
Simon Davidmann Imperas
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