Yes, absolutely. Many vector models historically have been co-processors with their own internal status. RVV integration is also a major accomplishment. I was a part of that. However, a consensus with

I'm trying to set vill, and I can't think of a reliable way to do it. This comes up when OpenOCD (a debugger) connects to a RV32 target where vtype contains (for instance) 0x80000000. The user asks to

Hello all, Could somebody please comment on the basic options related to chaining vector loads? It is easy to see how arithmetic vector instructions can be chained together. However, if a vector load

hi Krste and all friends, Per my understanding, if I extend the vector architecture register number (to be larger than 32) and extend maximum LMUL value to be larger than 8, current vector extension (

Does a known-good guide exist for building riscv64 qemu to be able to run Vector instructions? From the main qemu repo, we are to build the riscv64-softmmu target and run the 64-bit Buildroot Image, a

I’ve made a frozen release of version 1.0 ready for public review. The release is tagged: https://github.com/riscv/riscv-v-spec/releases/tag/v1.0 and I’ve attached pdf below. The main repo has now adv

I've finally finished an extensive pass over the whole spec, and believe it should be ready for public review but given that it's late on a Friday, I would like to give at least one more sleep cycle b

If the vector operand to an integer vwredsum is long enough, 2*SEW will not be large enough to contain the result. I would interpret the spec to suggest that the low 2*SEW bits are written to the dest

It might be worth updating sections: 7.5 Vector Strided Instructions 7.6 Vector Indexed Instructions with the address calculations to specify the stride offsets and indexs and byte sized, rather than

Hi, Re-reading section 3.3.2 in the documentation (link), would like to propose adding goal, constraints, steps for implementing Fraction LMUL I think adding these would really help clarify both the V

Hi Mick, The vector 0.7.1 version has been implemented in T-Head Xuantie c910v CPU and AllWinner D1 Soc. If that's what you want or If you want to use the QEMU upstream currently, I can give you some

I see that section 7.5 of the vector spec currently says: When rs2=x0, then an implementation is allowed, but not required, to perform fewer memory operations than the number of active elements, and m

Hi, The way 18.1 and 18.2 currently read in the V spec is a bit confusing. It defines Zve as "Vector extensions for Embedded Processors", and V as a "Vector Extension for Application Processor". 1) Pr

Date: 2021/07/09 Task Group: Vector Extension Chair: Krste Asanovic Vice-Chair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscv-v-spec We had a short mee

We’ll meet tomorrow to see if there are any remaining concerns before going Into public review, Krste

For discussion: The text states: reporting an error and terminating execution is the appropriate response. Issue #598 to be resolved after v1.0 and issue #364 which is tagged with "resolve for v1.0" a

Date: 2021/07/02 Task Group: Vector Extension Chair: Krste Asanovic Vice-Chair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscv-v-spec We discussed sever

Based on feedback, we'll have a vector TG meeting tomorrow to address concerns. Details in usual place in Google calendar, Krste

Hi everyone, Are there any plans for a cut-down configuration of the vector extension suitable for embedded cores? It seems that the 32x128-bit register file is suitable for application class cores bu

There have been no substantial objections raised on the v1.0-rc1 draft, so I will cancel the meeting tomorrow. There are some minor suggestions and edits (thank you!), and I will incorporate these int