Hi, The way 18.1 and 18.2 currently read in the V spec is a bit confusing. It defines Zve as "Vector extensions for Embedded Processors", and V as a "Vector Extension for Application Processor". 1) Pr

Date: 2021/07/09 Task Group: Vector Extension Chair: Krste Asanovic Vice-Chair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscv-v-spec We had a short mee

We’ll meet tomorrow to see if there are any remaining concerns before going Into public review, Krste

For discussion: The text states: reporting an error and terminating execution is the appropriate response. Issue #598 to be resolved after v1.0 and issue #364 which is tagged with "resolve for v1.0" a

Date: 2021/07/02 Task Group: Vector Extension Chair: Krste Asanovic Vice-Chair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscv-v-spec We discussed sever

Based on feedback, we'll have a vector TG meeting tomorrow to address concerns. Details in usual place in Google calendar, Krste

Hi everyone, Are there any plans for a cut-down configuration of the vector extension suitable for embedded cores? It seems that the 32x128-bit register file is suitable for application class cores bu

There have been no substantial objections raised on the v1.0-rc1 draft, so I will cancel the meeting tomorrow. There are some minor suggestions and edits (thank you!), and I will incorporate these int

Unless there are significant issues raised by the group on the v1.0-rc1 spec, the intent is to go into public review on June 25th, so please make sure to give any feedback before then. There are a few

Dear Craig and Roger, ​ ​Thanks a lot for providing me goodsolution. I have tried them, they are all good solutions of upsample application. ​ ​ But, when it comes to other applications, such as zip/u

Andrew Waterman called Thursday and we discussed many issues including challenges with Issues in Github. We determined that both were unaware of some relevant aspects [neither of us intentionally blin

Hi, all I encountered a difficulty of applying "vrgather" instruction recently. The details are shown blow: The date from source should be duplicated as pair in a upsample application. Eg: src = [0, 1

I've just tagged the first release candidate for v1.0 of the vector spec in github. PDF attached below. I've included the TG agreed updates and handled almost all of the outstanding issues for v1.0. T

see github issue #550 Krste

This is a good question. So if the RVM22 profile requires VLEN=32, ELEN=64, LMUL=8 then the vector registers will have the same amount of state as ARM MVE. Tariq

Hi, Krste: The RISC-V V TG have the plan to support a lowcost vector extension in RVMxx profile? Best Regards Shaofei 2021.6.3 -----邮件原件----- 发件人: krste@... [mailto:krste@...] 发送时间: 2021年6月3日 2:13 收件人

Hi all, I could not find any instruction that immediately computes this. Apologies if I missed the obvious here. Two options came to mind: vpopc.m and check whether the result is 0 (all zeros) or VLMA

Hi, We would like to announce that the RISC-V V-extension v0.10 has been implemented in LLVM and the work has been committed upstream. Barcelona Supercomputing Center (BSC), Codeplay Software, and SiF

Hi, I’m starting a project where we want to use vector intrinsics and generate both 64b and 32b code (for RV64 and RV32). It looks line the best way to do this right now is with GCC, where we were abl

https://erik-engheim.medium.com/arm-vs-risc-v-vector-extensions-992f201f402f Rather superficial - all about how hard it is for a person to program in assembly language, rather than how a compiler can