Basic options for chaining vector loads? 2 messages By Arjan Bink ·
Is it safe to extend LMUL's maximum value based on current rc2 version? 3 messages By Feng Chuang ·
Configuring qemu for Vector Extension 12 messages By Mick Thomas Lim ·
Vector 1.0 ready for public review By Krste Asanovic ·
Vector spec v1.0-rc2 By Krste Asanovic ·
vwredsum 3 messages By Earl Killian ·
Specify byte index/offset for Strided/Indexed instructions. Minor document improvement RISC-V "V" Vector Extension Version 1.0-rc1-20210608 By Tony Cole ·
Clarification of Fractional LMUL requirements, and the storage/derivation of ELEN/SEWLMUL1MAX values 2 messages By Gregory Kielian ·
回复:[RISC-V] [tech-vector-ext] Configuring qemu for Vector Extension By LIU Zhiwei ·
Multiple accesses required to the same location for strided memory accesses By Bill Huffman ·
Zve should be a strict subset of V, use new option to relax VLEN 5 messages By Guy Lemieux ·
Vector TG Meeting Minutes 2021/07/09 By Krste Asanovic ·
Vector TG Meeting tomorrow 5 messages By Krste Asanovic ·
Vector TG Meeting tomorrow - imprecise trap description/use. By David Horner ·
Vector TG meeting minutes 2021/07/02 2 messages By Krste Asanovic ·
Vector TG meeting tomorrow usual time slot By Krste Asanovic ·
Smaller embedded version of the Vector extension 34 messages By Tariq Kurd ·
No vector TG meeting tomorrow - preparing to start public review 3 messages By Krste Asanovic ·
Potential Vector Task Group Meeting and v1.0-rc1 review reminder by June 25 By Krste Asanovic ·
回复:Re: 回复:[RISC-V] [tech-vector-ext] RISC-V Vector Spec version 1.0-rc1-20210608 6 messages By Linjie Yu ·