Hi, We would like to announce that the RISC-V V-extension v0.10 has been implemented in LLVM and the work has been committed upstream. Barcelona Supercomputing Center (BSC), Codeplay Software, and SiF

Hi, I’m starting a project where we want to use vector intrinsics and generate both 64b and 32b code (for RV64 and RV32). It looks line the best way to do this right now is with GCC, where we were abl

https://erik-engheim.medium.com/arm-vs-risc-v-vector-extensions-992f201f402f Rather superficial - all about how hard it is for a person to program in assembly language, rather than how a compiler can

Hi all, I’m still new to RISC-V and the Vector extensions, so forgive me if I’ve missed something, the following have been fixed or noted before. Also, am I sending this to the correct group for GCC R

Hi Vector Team, I’m new to RISC-V and the Vector extensions, so forgive me if I’ve missed something. I have searched the specs, emails and git hub issues, but not found anything on this: While writing

I haven’t seen any burning issues come by, and am still trying to clean up spec. So unless someone has agenda items, I’m canceling meeting tomorrow, Krste

I’m still working on spec cleanup and I don’ t have any major outstanding issues to discuss, so will cancel the TG meeting this week. Please bring up any burning issues on this mailing list, Krste

Date: 2021/03/26 Task Group: Vector Extension Chair: Krste Asanovic Vice-Chair: Roger Espasa Number of Attendees: ~10 Current issues on github: https://github.com/riscv/riscv-v-spec A short meeting di

We'll meet again in usual slot. The main discussion topic will be #545. Please read the issue thread on github. Summary: The proposal is to move vector AMOs from their current encoding to leave space

Date: 2021/03/19 Task Group: Vector Extension Chair: Krste Asanovic Vice-Chair: Roger Espasa Number of Attendees: ~16 Current issues on github: https://github.com/riscv/riscv-v-spec Issues discussed #

There are a few issues to discuss, so we’ll meet in the regular time slot on the calendar, Krste

I'm cancelling meeting again, as I still have not been able to clean spec. I realize it will be more efficient for folks to wait for a clean version for a complete read through. Few issues are being r

I'm still working through spec cleanup. The list and github has been quiet, and I have no new issues to raise, so I suggest we cancel this meeting and push out for a week. Krste

Date: 2021/02/19 Task Group: Vector Extension Chair: Krste Asanovic Vice-Chair: Roger Espasa Number of Attendees: ~23 Current issues on github: https://github.com/riscv/riscv-v-spec # Next Meeting/Fre

Hi everyone, I’ve updated the Zfinx spec to show which V-extension instructions are affected. https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc#vector Please review the list, and tell m

We’ll meet today in usual slot, details on Google calendar Agenda is to discuss any issues found while reading over the v0.10 spec. List and GitHub has been quite quiet, so this might be a short meeti

Date: 2020/12/18 Task Group: Vector Extension Chair: Krste Asanovic Co-Chair: Roger Espasa Number of Attendees: ~10 Current issues on github: https://github.com/riscv/riscv-v-spec Note: No more meetin

Hello, I've just joined the RISC-V technical community and the V Extension Task group. I have very substantial experience in careful technical documentation (I wrote the RFCs for gzip and DEFLATE, and

Date: 2021/02/05 Task Group: Vector Extension Chair: Krste Asanovic Vice-Chair: Roger Espasa Number of Attendees: ~16 Current issues on github: https://github.com/riscv/riscv-v-spec # Next Meeting It

We’ll meet tomorrow in usual slot per TG calendar. The agenda is to review any feedback on the 0.10 spec and then to proceed through any outstanding issues, Krste