
回复: [RISCV] [techvectorext] What is the plan for rvv v1.0
That is exactly what I want. Thanks Mark. Weiwei 发件人: techvectorext@... <techvectorext@...> 代表 mark 发送时间: 2020年11月25日 23:13 收件人: Wang Weiwei <Weiwei.Wang@...> 抄送: vector <techvectorext@...> 主题:
That is exactly what I want. Thanks Mark. Weiwei 发件人: techvectorext@... <techvectorext@...> 代表 mark 发送时间: 2020年11月25日 23:13 收件人: Wang Weiwei <Weiwei.Wang@...> 抄送: vector <techvectorext@...> 主题:

By
Wang Weiwei
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What is the plan for rvv v1.0 2 messages
Hi Krste and Andrew, What is the rough plan for rvv v1.0 release? I searched vectorext mailing list but can’t find the info I want. Thanks Weiwei
Hi Krste and Andrew, What is the rough plan for rvv v1.0 release? I searched vectorext mailing list but can’t find the info I want. Thanks Weiwei

By
Wang Weiwei
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next vector meeting in 7 hours
I think we'll be spending a chunk of time on mask layout and implementation issues. See you then, Krste
I think we'll be spending a chunk of time on mask layout and implementation issues. See you then, Krste

By
Krste Asanovic
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rename vfrece7/vfrsqrte7 to vfrec7 and vfrsqrt7 2 messages
This is issue #601. It was pointed out that *e7 (estimate to 7 bits) suffix on mnemonic is easily confused with e32 (element size 32) on other mnemonics. This is probably one we can handle on email th
This is issue #601. It was pointed out that *e7 (estimate to 7 bits) suffix on mnemonic is easily confused with e32 (element size 32) on other mnemonics. This is probably one we can handle on email th

By
Krste Asanovic
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Vector TG minutes 2020/11/13 meeting
Date: 2020/11/13 Task Group: Vector Extension Chair: Krste Asanovic CoChair: Roger Espasa Number of Attendees: ~22 Current issues on github: https://github.com/riscv/riscvvspec Issues discussed: #
Date: 2020/11/13 Task Group: Vector Extension Chair: Krste Asanovic CoChair: Roger Espasa Number of Attendees: ~22 Current issues on github: https://github.com/riscv/riscvvspec Issues discussed: #

By
Krste Asanovic
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HalfPrecision, BFloat16, and Other Float Encoding: Reference Model Recommendations from Task Group 2 messages
In support of Open Source Software and publicly released modeling schemes, does the Vector Task Group have a recommendation for arithmetic reference? The published ISSs can provide checking results fr
In support of Open Source Software and publicly released modeling schemes, does the Vector Task Group have a recommendation for arithmetic reference? The published ISSs can provide checking results fr

By
CDS
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Vector TG minutes from 2020/11/6 meeting
Also, reminder we'll be meeting tomorrow (Friday Nov 13) as per calendar entry (7 hours from now), Krste Date: 2020/11/06 Task Group: Vector Extension Chair: Krste Asanovic CoChair: Roger Espasa Numb
Also, reminder we'll be meeting tomorrow (Friday Nov 13) as per calendar entry (7 hours from now), Krste Date: 2020/11/06 Task Group: Vector Extension Chair: Krste Asanovic CoChair: Roger Espasa Numb

By
Krste Asanovic
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vector strided stores when rs1=x0 8 messages
Also on github as issue #595 In our earlier TG discussion in 9/18 meeting, we were in favor of allowing vector strided load instructions with rs1=x0 to perform fewer memory accesses than the number of
Also on github as issue #595 In our earlier TG discussion in 9/18 meeting, we were in favor of allowing vector strided load instructions with rs1=x0 to perform fewer memory accesses than the number of

By
Krste Asanovic
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Vector Byte Arrangement in Wide Implementations 10 messages
I've been thinking through the cases where a wide implementation that wants "slices" could have to introduce a hiccup to rearrange bytes because of an EEW change (since SLEN is gone). The ones I know
I've been thinking through the cases where a wide implementation that wants "slices" could have to introduce a hiccup to rearrange bytes because of an EEW change (since SLEN is gone). The ones I know

By
Bill Huffman
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reminder, Vector task group meeting Friday
We'll meet per the calendar entry. Agenda is to go over any remaining unsettled open issues, Krste
We'll meet per the calendar entry. Agenda is to go over any remaining unsettled open issues, Krste

By
Krste Asanovic
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[RISCV] [tech] [RISCV] [tech*] STRATEGIC FEATURE COEXISTANCE was:([techfastint] usefulness of PUSHINT/POPINT from [techcodesize])
Thanks Tim, I think that sums it up nicely. I just wanted to put a pointer out to the original post that I made on isadev regarding opcode sharing / management: https://groups.google.com/a/groups.ris
Thanks Tim, I think that sums it up nicely. I just wanted to put a pointer out to the original post that I made on isadev regarding opcode sharing / management: https://groups.google.com/a/groups.ris

By
Guy Lemieux
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Sparse MatrixVector Multiply (again) and BitVector Compression 13 messages
I am now investigating how to efficiently implement sparse matrix X (dense) vector multiplications (spMV) using RISCV vectors using bitvector format of compressing the sparse matrix. The inner loop o
I am now investigating how to efficiently implement sparse matrix X (dense) vector multiplications (spMV) using RISCV vectors using bitvector format of compressing the sparse matrix. The inner loop o

By
Nagendra Gulur
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[RISCV] [tech*] STRATEGIC FEATURE COEXISTANCE was:([techfastint] usefulness of PUSHINT/POPINT from [techcodesize]) 4 messages
These are all important considerations. However, what they have in common when considering Allen's question: is that they are all tactical considerations are in the context of our current framework of
These are all important considerations. However, what they have in common when considering Allen's question: is that they are all tactical considerations are in the context of our current framework of

By
David Horner
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change "raise illegal instruction" > "reserved" for static encodings 3 messages
I'm working through updates to vector spec, and one part of clean up is changing text where it has mandatory raising of illegal instruction exceptions on unsupported encodings to instead state the enc
I'm working through updates to vector spec, and one part of clean up is changing text where it has mandatory raising of illegal instruction exceptions on unsupported encodings to instead state the enc

By
Krste Asanovic
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Vector Task Group minutes, 2020/10/23
Reminder: No meeting next Friday October 30. Date: 2020/10/23 Task Group: Vector Extension Chair: Krste Asanovic CoChair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://githu
Reminder: No meeting next Friday October 30. Date: 2020/10/23 Task Group: Vector Extension Chair: Krste Asanovic CoChair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://githu

By
Krste Asanovic
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[RISCV] [techcmo] Faultonfirst should be allowed to return randomly on nonfaults (also, running SIMT code on vector ISA) 25 messages
Forwarding this to techvectorext; couple comments below. Indeed, I've found other microarchitectural reasons to favor this approach (e.g., speculating through maskregister values). Enumerating all
Forwarding this to techvectorext; couple comments below. Indeed, I've found other microarchitectural reasons to favor this approach (e.g., speculating through maskregister values). Enumerating all

By
Andrew Waterman
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Vector TG meeting minutes 2020/10/16
Date: 2020/10/16 Task Group: Vector Extension Chair: Krste Asanovic CoChair: Roger Espasa Number of Attendees: ~16 Current issues on github: https://github.com/riscv/riscvvspec # Definition of Done
Date: 2020/10/16 Task Group: Vector Extension Chair: Krste Asanovic CoChair: Roger Espasa Number of Attendees: ~16 Current issues on github: https://github.com/riscv/riscvvspec # Definition of Done

By
Krste Asanovic
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Sequence to insert an element 2 messages
Hi, what is a reasonable sequence to insert an element into an arbitrary position in the vector? I considered the following sequence (assume the input vector is v12) vid.v v1 vmseq.vx v0, v1, <index>
Hi, what is a reasonable sequence to insert an element into an arbitrary position in the vector? I considered the following sequence (assume the input vector is v12) vid.v v1 vmseq.vx v0, v1, <index>

By
Roger Ferrer Ibanez
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Vector TG minutes from 2020/10/9 meeting
Date: 2020/10/9 Task Group: Vector Extension Chair: Krste Asanovic CoChair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscvvspec # 576 vlsegff excepti
Date: 2020/10/9 Task Group: Vector Extension Chair: Krste Asanovic CoChair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscvvspec # 576 vlsegff excepti

By
Krste Asanovic
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Minutes from 2020/10/2 meeting
Date: 2020/10/2 Task Group: Vector Extension Chair: Krste Asanovic CoChair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscvvspec Issues discussed; # I
Date: 2020/10/2 Task Group: Vector Extension Chair: Krste Asanovic CoChair: Roger Espasa Number of Attendees: ~12 Current issues on github: https://github.com/riscv/riscvvspec Issues discussed; # I

By
Krste Asanovic
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